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| s1d13a05 lcd/usb companion chip hardware functional specification document number: x40a-a-001-07 status: revision 7.7 issue date: 2012/02/27 ? seiko epson corporation 2002 - 2012. inc. all rights reserved. information in this document is subject to change without noti ce. you may download and use this document, but only for your own use in evaluating seiko epson/epson products. you may not modify the document. epson research and development, inc. disclaims any representation that the contents of this document are accurate or current. the programs/technologies described in this document may contain material protected under u.s. and/or international patent laws. epson is a registered trademark of seiko epson corporation. all other trademarks are the property of their respective owners
page 2 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 epson research and development page 3 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 overview description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 integrated frame buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 display support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 display features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 usb device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 2d acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 typical system implementation diagrams . . . . . . . . . . . . . . . . . . . . . . 11 3.1 typical system diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 usb interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 pinout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 pfbga 121-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.2 lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.3 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.4 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.5 power and ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 4.3 summary of configuration options . . . . . . . . . . . . . . . . . . . . . . 25 4.4 host bus interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 lcd interface pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 d.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 a.c. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.1 input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.2 internal clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 reset# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 cpu interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 generic #1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 page 4 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.2 generic #2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3.3 hitachi sh-3 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.3.4 hitachi sh-4 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3.5 motorola mc68k #1 interface timing . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.6 motorola mc68k #2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.7 motorola redcap2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3.8 motorola dragonball interface timing with dtack . . . . . . . . . . . . . . . . 46 6.3.9 motorola dragonball interface timing w/o dtack . . . . . . . . . . . . . . . . . 48 6.4 lcd power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.4.1 passive/tft power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.2 passive/tft power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5 display interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.5.1 generic stn panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.5.2 single monochrome 4-bit panel timing . . . . . . . . . . . . . . . . . . . . . . . 54 6.5.3 single monochrome 8-bit panel timing . . . . . . . . . . . . . . . . . . . . . . . 56 6.5.4 single color 4-bit panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.5.5 single color 8-bit panel timing (format 1) . . . . . . . . . . . . . . . . . . . . . 60 6.5.6 single color 8-bit panel timing (format 2) . . . . . . . . . . . . . . . . . . . . . 62 6.5.7 single color 16-bit panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.5.8 generic tft panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.5.9 9/12/18-bit tft panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.5.10 sharp hr-tft panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.5.11 casio tft panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.5.12 tft type 2 panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.5.13 tft type 3 panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.5.14 tft type 4 panel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.6 usb timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 7 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.1 clock descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 7.1.1 bclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.2 mclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.1.3 pclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.1.4 pwmclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.2 clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 7.3 clocks versus functions . . . . . . . . . . . . . . . . . . . . . . . . . . .89 8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 8.1 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 8.2 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 8.3 lcd register descriptions (offset = 0h) . . . . . . . . . . . . . . . . . . . .93 epson research and development page 5 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.3.1 read-only configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.3.2 clock configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3.3 panel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.3.4 look-up table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3.5 display mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.3.6 picture-in-picture plus (pip+) registers . . . . . . . . . . . . . . . . . . . . . . . 110 8.3.7 miscellaneous registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.3.8 extended panel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.4 usb registers (offset = 4000h) . . . . . . . . . . . . . . . . . . . . . . . 1 35 8.5 2d acceleration (bitblt) registers (offset = 8000h) . . . . . . . . . . . . . . 153 8.6 2d accelerator (bitblt) data register descriptions . . . . . . . . . . . . . . . 160 9 2d accelerator (bitblt) engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 9.2 bitblt operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10 frame rate calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 11 display data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12 look-up table architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.1 monochrome modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.2 color modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 13.1 concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 13.2 90 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 13.2.1 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.3 180 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.3.1 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.4 270 swivelview? . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13.4.1 register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14 picture-in-picture plus (pip+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.1 concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.2 with swivelview enabled . . . . . . . . . . . . . . . . . . . . . . . . .176 14.2.1 swivelview 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 14.2.2 swivelview 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.2.3 swivelview 270 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15 power save mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 16 usb considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.1 usb oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 17 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 page 6 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 19 sales and technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 epson research and development page 7 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1 introduction 1.1 scope this is the hardware functional specification for the s1d13a05 lcd/usb companion chip. included in this document are timing diagrams, ac and dc characteristics, register descriptions, and power management descriptions. this document is intended for two audiences: video subsystem designers and software developers. this document is updated as appropriate. please check for the latest revision of this document before beginning any development. the latest revision can be downloaded at www.erd.epson.com. we appreciate your comments on our documentation. please contact us via email at documentation@erd.epson.com. 1.2 overview description the s1d13a05 is an lcd/usb solution designed for seamless connection to a wide variety of microprocessors. the s1d13a05 integrates a usb slave controller and an lcd graphics controller with an embedded 256k byte sram display buffer. the lcd controller supports all standard panel types and multiple tft types eliminating the need for an external timing control ic. the s1d13a05 includes a hardware acceleration engine to greatly improve screen drawing functions and the built-in usb controller provides revision 1.1 compliance for applications requiring a usb client. this high level of integration provides a low cost, low power, single chip solution to meet the demands of embedded markets requiring usb client support, such as mobile communications devices and palm- size pcs. the s1d13a05 utilizes a guaranteed low-latency cpu architecture that provides support for microprocessors without ready/wait# handshaking signals. the 32-bit internal data path, write buffer and the hardware acceleration engine provide high performance bandwidth into display memory allowing for fast display updates. additionally, products requiring a rotated display can take advantage of the swivelview tm feature which provides hardware rotation of the display memory transparent to the software application. the s1d13a05 also provides support for ?picture-in-picture plus? (a variable size overlay window). the s1d13a05, with its integrated usb client, provides impressive support for palm os ? handhelds. however, its impartiality to cpu type or operating system makes it an ideal display solution for a wide variety of applications. page 8 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 2 features 2.1 integrated frame buffer ? embedded 256k byte sram display buffer. 2.2 cpu interface ? direct support of the following interfaces: hitachi sh-4 / sh-3. motorola m68xxx (redcap2, dragonball, coldfire). motorola dragonball sz support (66mhz). motorola ?redcap2? - no wait# signal. generic mpu bus interface with programmable ready (wait#). ? ?fixed? low-latency cpu access times. ? registers are memory-mapped - m/r# input selects between memory and register address space. ? the complete 256k byte display buffer is directly and contiguously available through the 18-bit address bus. 2.3 display support ? single-panel, single drive passive displays. ? 4/8-bit monochrome lcd interface. ? 4/8/16-bit color lcd interface. ? active matrix tft interface. ? 9/12/18-bit interface. ? extended tft interfaces (type 2, 3, 4) ? ?direct? support for 18-bit sharp hr-tft lcd (or compatible interfaces). ? ?direct? support for the casio tft lcd (or compatible interfaces). epson research and development page 9 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 2.4 display modes ? 1/2/4/8/16 bit-per-pixel (bpp) color depths. ? up to 64 gray shades on monochrome passive lcd panels. ? up to 64k colors on passive panels. ? up to 64k colors on active matrix lcd panels. ? example resolutions: 320x320 at a color depth of 16 bpp 160x160 at a color depth of 16 bpp (2 pages) 160x240 at a color depth of 16 bpp 2.5 display features ? swivelview?: 90, 180, 270 counter-clockwise hardware rotation of display image. ? picture-in-picture plus (pip + ): displays a variable size window overlaid over back- ground image. ? pixel doubling: independent control of both horizontal and vertical pixel doubling. ? example usage: 160x160 8 bpp can be expanded to 320x320 8 bpp without any addi- tional memory. ? supports all color depths. ? double buffering/multi-pages: provides smooth animation and instantaneous screen updates. 2.6 clock source ? three independent clock inputs: clki, clki2 and usbclk. ? flexible clock source selection: ? internal bus clock (bclk) selected from clki, clki/2, or clki2 ? internal memory clock (mclk) selected from bclk or bclk divide ratio (reg[04h) ? internal pixel clock (pclk) selected from clki, clki2, mclk, or bclk. pclk can also be divided down from source ? single clock input possible if usb support not required. 2.7 usb device ? usb client, revision 1.1 compliant. ? dedicated clock input: usbclk. ? 48mhz crystal oscillator for usbclk. page 10 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 2.8 2d acceleration ? 2d bitblt engine including: write bitblt transparent write bitblt move bitblt transparent move bitblt solid fill bitblt read bitblt pattern fill bitblt color expansion bitblt move bitblt with color expansion 2.9 miscellaneous ? software initiated video invert. ? software initiated power save mode. ? general purpose input/output pins are available. ? io operates at 3.3 volts 10%. ? core operates at 2.0 volts 10% or 2.5 volts 10%. ? 121-pin pfbga package. epson research and development page 11 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 3 typical system implementation diagrams 3.1 typical system diagrams. figure 3-1: typical system diagram (generic #1 bus) . figure 3-2: typical system diagram (generic #2 bus) s1d13a05 fpline fpframe fpshift drdy fpdat[15:0] clki2 oscillator fpline fpframe fpshift mod d[15:0] 16-bit generic #1 bus reset# d[15:0] rd0# wait# a[17:1] busclk rd/wr# ab[17:1] db[15:0] we1# rd# m/r# cs# clki wait# reset# a[27:18] csn# we1# gpio0 decoder we0# we0# single lcd display bias power vss rd1# ab0 bs# iovdd s1d13a05 fpline fpframe fpshift drdy fpdat[8:0] clki2 oscillator fpline fpframe fpshift drdy d[8:0] 9-bit generic #2 bus reset# d[15:0] rd# wait# a[17:0] busclk rd/wr# ab[17:0] db[15:0] we1# rd# m/r# cs# clki wait# reset# a[27:18] csn# bhe# gpio0 decoder we0# we# tft bias power bs# iovdd display page 12 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 . figure 3-3: typical system diagram (hitachi sh-4 bus) . figure 3-4: typical system diagram (hitachi sh-3 bus) s1d13a05 fpline fpframe fpshift drdy fpdat[9:0] fpline fpframe fpshift drdy d[9:0] 12-bit sh-4 bus reset# we0# d[15:0] bs# rd/wr# rd# rdy# a[17:1] ckio we0# rd/wr# ab[17:1] db[15:0] we1# bs# rd# m/r# cs# clki wait# reset# a[25:18] csn# we1# gpio0 clki2 oscillator tft display bias power fpdat12 fpdat15 d10 d11 decoder vss ab0 s1d13a05 fpline fpframe fpshift drdy fpdat[17:0] fpline fpframe fpshift drdy d[17:0] 18-bit sh-3 bus reset# we0# d[15:0] bs# rd/wr# rd# wait# a[17:1] ckio we0# rd/wr# ab[17:1] db[15:0] we1# bs# rd# m/r# cs# clki wait# reset# a[25:18] csn# we1# gpo0 clki2 oscillator tft display bias power decoder vss ab0 epson research and development page 13 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 . figure 3-5: typical system diagram (mc68k # 1, motorola 16-bit 68000) . figure 3-6: typical system diagram (mc68k #2, motorola 32-bit 68030) s1d13a05 fpline fpframe fpshift fpdat[17:0] lp sps clk d[17:0] 18-bit mc68k #1 bus reset# lds# d[15:0] as# r/w# dtack# a[17:1] clk ab0 rd/wr# ab[17:1] db[15:0] we1# bs# m/r# cs# clki wait# reset# a[23:18] fc0, fc1 decoder decoder uds# clki2 oscillator hr-tft display rd# we0# iovdd gpio0 gpio1 gpio2 gpio3 ps cls rev spl s1d13a05 mc68k #2 bus reset# siz0 d[31:16] as# r/w# siz1 dsack1# a[17:0] clk we0# rd/wr# ab[17:0] db[15:0] we1# bs# rd# m/r# cs# clki wait# reset# a[31:18] fc0, fc1 decoder decoder ds# clki2 oscillator fpline fpframe fpshift fpdat[17:0] lp sps clk d[17:0] 18-bit hr-tft display gpio0 gpio1 gpio2 gpio3 ps cls rev spl page 14 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 . figure 3-7: typical system diagram (motorola redcap2 bus) . figure 3-8: typical system diagram (motorola mc68ez328/mc68vz328 ?dragonball? bus) s1d13a05 fpframe fpshift fpline drdy fpdat[7:4] fpframe fpshift fpline mod d[3:0] 4-bit redcap2 bus reset_out eb1 d[15:0] r/w oe a[17:1] clk we0# rd/wr# ab[17:1] db[15:0] we1# rd# m/r# cs# clki reset# a[21:18] decoder eb0 gpio0 clki2 oscillator single lcd bias power csn *note: csn# can be any of cs0-cs4 display bs# vss ab0 iovdd s1d13a05 fpframe fpshift fpline drdy fpdat[7:0] fpframe fpshift fpline mod d[7:0] 8-bit mc68ez328/ reset d[15:0] oe dtack a[17:1] clko rd/wr# ab[17:1] db[15:0] we1# rd# m/r# cs# clki wait# reset# a[25:18] cs x uwe gpio0 decoder we0# lwe iovdd clki2 oscillator single bias power bs# dragonball bus lcd display mc68vz328 vss ab0 epson research and development page 15 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 3.2 usb interface figure 3-9: usb typical implementation usbdp usbdm s1d13a05 usb socket usbdetect usbpup dm dp vbus gnd vss iovdd nncd5.6lg 150k 300k 1.5k 20 20 300k full speed device overvoltage protection esd protection (gpio5) (gpio4) (gpio7) (gpio6) page 16 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 4 pins 4.1 pinout diagrams 4.1.1 pfbga 121-pin figure 4-1: pinout diagram - pfbga 121-pin table 4-1: pfbga 121-pin mapping l nc iovdd db7 db3 db0 gpio7 gpio3 gpio0 iovdd corevdd nc k gpo0 vss db8 db4 db1 gpio6 gpio2 irq drdy vss gpo6 j gpo1 db9 db6 db5 db2 gpo3 gpio1 usbclk fpframe corevdd gpo7 h db12 db11 db10 db13 gpo2 iovdd gpio4 gpo5 fpline fpshift fpdat0 g wait# db15 db14 iovdd vss gpio5 fpdat5 fpdat1 fpdat2 fpdat3 fpdat4 f reset# vss rd/wr# we1# clki gpo4 fpdat8 fpdat6 vss fpdat7 iovdd e rd# bs# m/r# cs# we0# ab13 testen fpdat9 fpdat12 fpdat11 fpdat10 d ab0 ab1 ab2 ab8 ab12 ab17 cnf3 fpdat13 fpdat16 fpdat15 fpdat14 c usbosco corevdd ab3 ab6 ab9 ab16 cnf2 cnf5 cnf6 fpdat17 gpo8 b usbosci vss ab5 gpo10 ab10 ab14 cnf1 cnf4 clki2 vss gpo9 a nc corevdd ab4 ab7 ab11 ab15 cnf0 nc pwmout iovdd nc 1234567891011 l k j h g f e d c b a 1234567891011 bottom view epson research and development page 17 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 4.2 pin descriptions key: a lvttl is low voltage ttl. 4.2.1 host interface i = input o=output io = bi-directional (input/output) p=power pin ci = cmos input li = lvttl a input lb2a = lvttl io buffer (6ma/-6ma@3.3v) lb3p = low noise lvttl io buffer (6ma/-6ma@3.3v) lo3 = low noise lvttl output buffer (3ma/-3ma@3.3v) lb3m = low noise lvttl io buffer with input mask (3ma/-3ma@3.3v) t1 = test mode control input with pull-down resistor (typical value of 50k at 3.3v) hi-z = high impedance cus = custom cell type table 4-2: host interface pin descriptions pin name pfbga pin # i/o type (see key above) reset# state description ab0 d1 li ? this input pin has multiple functions. ? for generic #1, this pin is not used and should be connected to vss. ? for generic #2, this pin inputs system address bit 0 (a0). ? for sh-3/sh-4, this pin is not used and should be connected to vss. ? for mc68k #1, this pin inputs the lower data strobe (lds#). ? for mc68k #2, this pin inputs system address bit 0 (a0). ? for redcap2, this pin is not used and should be connected to vss. ? for dragonball, this pin is not used and should be connected to vss. ab[17:1] d6,c6,a6, b6,e6,d5, a5,b5,c5, d4,a4,c4, b3,a3,c3, d3,d2 ci ? system address bus bits 17-1. db[15:0] g2, g3, h4, h1, h2, h3, j2, k3, l3, j3, j4, k4, l4, j5, k5, l5 lb2a hi-z input data from the system data bus. ? for generic #1, these pins are connected to d[15:0]. ? for generic #2, these pins are connected to d[15:0]. ? for sh-3/sh-4, these pins are connected to d[15:0]. ? for mc68k #1, these pins are connected to d[15:0]. ? for mc68k #2, these pins are connected to d[31:16] for a 32-bit device (e.g. mc68030) or d[15:0] for a 16-bit device (e.g. mc68340). ? for redcap2, these pins are connected to d[15:0]. ? for dragonball, these pins are connected to d[15:0]. page 18 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 we0# e5 li ? this input pin has multiple functions. ? for generic #1, this pin inputs the write enable signal for the lower data byte (we0#). ? for generic #2, this pin inputs the write enable signal (we#) ? for sh-3/sh-4, this pin inputs the write enable signal for data byte 0 (we0#). ? for mc68k #1, this pin must be tied to io v dd ? for mc68k #2, this pin inputs the bus size bit 0 (siz0). ? for redcap2, this pin inputs the byte enable signal for the d[7:0] data byte (eb1 ). ? for dragonball, this pin inputs the byte enable signal for the d[7:0] data byte (lwe ). we1# f4 li ? this input pin has multiple functions. ? for generic #1, this pin inputs the write enable signal for the upper data byte (we1#). ? for generic #2, this pin inputs the byte enable signal for the high data byte (bhe#). ? for sh-3/sh-4, this pin inputs the write enable signal for data byte 1 (we1#). ? for mc68k #1, this pin inputs the upper data strobe (uds#). ? for mc68k #2, this pin inputs the data strobe (ds#). ? for redcap2, this pin inputs the byte enable signal for the d[15:8] data byte (eb0 ). ? for dragonball, this pin inputs the byte enable signal for the d[15:8] data byte (uwe ). cs# e4 ci ? chip select input. m/r# e3 li ? this input pin is used to select between the display buffer and register address spaces of the s1d13a05. m/r# is set high to access the display buffer and low to access the registers. bs# e2 li ? this input pin has multiple functions. ? for generic #1, this pin must be tied to io v dd . ? for generic #2, this pin must be tied to io v dd . ? for sh-3/sh-4, this pin inputs the bus start signal (bs#). ? for mc68k #1, this pin inputs the address strobe (as#). ? for mc68k #2, this pin inputs the address strobe (as#). ? for redcap2, this pin must be tied to io v dd . ? for dragonball, this pin must be tied to io v dd . table 4-2: host interface pin descriptions pin name pfbga pin # i/o type (see key above) reset# state description epson research and development page 19 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 rd/wr# f3 li ? this input pin has multiple functions. ? for generic #1, this pin inputs the read command for the upper data byte (rd1#). ? for generic #2, this pin must be tied to io v dd . ? for sh-3/sh-4, this pin inputs the rd/wr# signal. the s1d13a05 needs this signal for early decode of the bus cycle. ? for mc68k #1, this pin inputs the r/w# signal. ? for mc68k #2, this pin inputs the r/w# signal. ? for redcap2, this pin inputs the r/w signal. ? for dragonball, this pin must be tied to io v dd . rd# e1 li ? this input pin has multiple functions. ? for generic #1, this pin inputs the read command for the lower data byte (rd0#). ? for generic #2, this pin inputs the read command (rd#). ? for sh-3/sh-4, this pin inputs the read signal (rd#). ? for mc68k #1, this pin must be tied to io v dd . ? for mc68k #2, this pin inputs the bus size bit 1 (siz1). ? for redcap2, this pin inputs the output enable (oe ). ? for dragonball, this pin inputs the output enable (oe ). wait# g1 lb2a hi-z during a data transfer, this output pin is driven active to force the system to insert wait states. it is driven inactive to indicate the completion of a data transfer. wait# is released to the high impedance state after the data transfer is complete. its active polarity is configurable. ? for generic #1, this pin outputs the wait signal (wait#). ? for generic #2, this pin outputs the wait signal (wait#). ? for sh-3 mode, this pin outputs the wait request signal (wait#). ? for sh-4 mode, this pin outputs the device ready signal (rdy#). ? for mc68k #1, this pin outputs the data transfer acknowledge signal (dtack#). ? for mc68k #2, this pin outputs the data transfer and size acknowledge bit 1 (dsack1#). ? for redcap2, this pin is unused (hi-z). ? for dragonball, this pin outputs the data transfer acknowledge signal (dtack ). note: this pin should be tied to the inactive voltage level as selected by cnf5, using a pull-up or pull-down resistor. if cnf5 = 1, the wait# pin should be tied low using a pull-down resistor. if cnf5 = 0, the wait# pin should be tied high using a pull-up resistor. if wait# is not used, this pin should be tied either high or low using a pull-up or pull-down resistor. reset# f1 li ? active low input to set all internal registers to the default state and to force all signals to their inactive states. table 4-2: host interface pin descriptions pin name pfbga pin # i/o type (see key above) reset# state description page 20 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 4.2.2 lcd interface table 4-3: lcd interface pin descriptions pin name pfbga pin# i/o type (see key above) reset# state description fpdat[17:0] c10,d9,d10, d11,d8,e9, e10,e11, e8,f7,f10, f8,g7,g11, g10,g9,g8, h11 lb3p 0 panel data bits 17-0. fpframe j9 lb3p 0 this output pin has multiple functions. ?frame pulse ? sps for hr-tft ?gsrt for casio ? stv for tft type 2 ? stv for tft type 3 fpline h9 lb3p 0 this output pin has multiple functions. ?line pulse ? lp for hr-tft ? gpck for casio ? stb for tft type 2 ? lp for tft type 3 fpshift h10 lb3p 0 this output pin has multiple functions. ? shift clock ? dclk for hr-tft ?clk for casio ? clk for tft type 2 ? cph for tft type 3 drdy k9 lo3 0 this output pin has multiple functions. ? lcd backplane bias signal (mod) for all other lcd panels ? 2nd shift clock (fpshift2) for passive lcd with format 1 interface ? display enable (drdy) for tft panels ? inv for tft type 2/3 ? drdy for tft type 4 ? general purpose output gpo0 k1 lo3 0 this is a general purpose output gpo1 j1 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as vcom ? general purpose output bit otherwise gpo2 h5 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as xoev ? general purpose output bit otherwise gpo3 j6 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as cmd ? general purpose output bit otherwise epson research and development page 21 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 gpo4 f6 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as pclk1 ? general purpose output bit otherwise gpo5 h8 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as pclk2 ? general purpose output bit otherwise gpo6 k11 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as xresh ? general purpose output bit otherwise gpo7 j11 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as xresv ? general purpose output bit otherwise gpo8 c11 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as xohv ? general purpose output bit otherwise gpo9 b11 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as xstby ? general purpose output bit otherwise gpo10 b4 lo3 0 this output pin has multiple functions. ? when in tft type 3 mode, operates as pmde ? general purpose output bit otherwise gpio0 l8 lb3m ? this pin has multiple functions. ? ps for hr-tft ?pol for casio ?vclk for tft type 2 ? cpv for tft type 3 ? general purpose io pin 0 (gpio0) when this pin is used for the above display modes, it must be configured as an output using reg[64h] after every reset. otherwise, it defaults to a hi-z state after every reset and must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain. gpio1 j7 lb3m ? this pin has multiple functions. ? cls for hr-tft ?gres for casio ? ap for tft type 2 ? oe for tft type 3 ? general purpose io pin 1 (gpio1) when this pin is used for the above display modes, it must be configured as an output using reg[64h] after every reset. otherwise, it defaults to a hi-z state after every reset and must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain. table 4-3: lcd interface pin descriptions pin name pfbga pin# i/o type (see key above) reset# state description page 22 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 gpio2 k7 lb3m ? this pin has multiple functions. ? rev for hr-tft ?frp for casio ? pol for tft type 2/3 ? general purpose io pin 2 (gpio2) when this pin is used for the above display modes, it must be configured as an output using reg[64h] after every reset. otherwise, it defaults to a hi-z state after every reset and must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain. gpio3 l7 lb3m ? this pin has multiple functions. ? spl for hr-tft ?sth for casio ? sth for tft type 2 ?eio for tft type 3 ? general purpose io pin 3 (gpio3) when this pin is used for the above display modes, it must be configured as an output using reg[64h] after every reset. otherwise, it defaults to a hi-z state after every reset and must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain. gpio4 h7 lb3m ? this pin has multiple functions. ? usbpup ? general purpose io pin 4 (gpio4) this pin is hi-z after every reset and must either be configured as an output using reg[64h] or be pulled high or low externally to avoid unnecessary current drain. gpio5 g6 lb3m ? this pin has multiple functions. ? usbdetect ? general purpose io pin 5 (gpio5) this pin always defaults as an input. when not used as a usbdetect pin, it must either be configured as an output using reg[64h] or be pulled high or low externally to avoid unnecessary current drain. table 4-3: lcd interface pin descriptions pin name pfbga pin# i/o type (see key above) reset# state description epson research and development page 23 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 gpio6 k6 cus ? this pin has multiple functions. ? usbdm ? general purpose io pin 6 (gpio6) when not used as a usb connection, this pin defaults to a hi-z state after every reset and must either be configured as an output using reg[64h] or be pulled high or low externally to avoid unnecessary current drain. gpio7 l6 cus ? this pin has multiple functions. ? usbdp ? general purpose io pin 7 when not used as a usb connection, this pin defaults to a hi-z state after every reset and must either be configured as an output using reg[64h] or be pulled high or low externally to avoid unnecessary current drain. irq k8 lo3 0 this output pin is the irq pin for usb. when irq is activated, an active high pulse is generated and stays high until the irq is serviced by software at reg[404ah] or reg[404ch]. pwmout a9 lo3 0 this pin has multiple functions. ? pwm clock output ? general purpose output table 4-3: lcd interface pin descriptions pin name pfbga pin# i/o type (see key above) reset# state description page 24 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 4.2.3 clock input 4.2.4 miscellaneous 4.2.5 power and ground table 4-4: clock input pin descriptions pin name pfbga pin# i/o type (see key above) reset# state description clki f5 ci ? typically used as input clock source for bus clock and memory clock clki2 b9 ci ? optionally used as input clock source for pixel clock usbclk j8 ci ? used as input clock source for usb. note: if this pin is not connected to an input clock source, this pin must be connected to vss. usbosci b1 i ? usb crystal oscillator feedback input from crystal. for an example implementation circuit using a crystal oscillator, see section 16.1, ?usb oscillator circuit? on page 179. note: if this pin is not connected to a usb crystal oscillator, this pin must be connected to vss. usbosco c1 o ? usb crystal oscillator output to crystal. for an example implementation circuit using a crystal oscillator, see section 16.1, ?usb oscillator circuit? on page 179. table 4-5: miscellaneous pin descriptions pin name pfbga pin# i/o type (see key above) reset# state description cnf[6:0] c9,c8,b8, d7,c7,b7, a7 ci ? these inputs are used to configure the s1d13a05 - see table 4-7: ?summary of power-on/reset options,? on page 25. note: these pins are used for configuration of the s1d13a05 and must be connected directly to io v dd or v ss . testen e7 t1 ? test enable input used for production test only (has type 1 pull-down resistor with a typical value of 50k at 3.3v). note: this pin must be left un-connected. table 4-6: power and ground pin descriptions pin name pfbga pin# i/o type (see key above) reset# state description iovdd l2,g4,h6, l9,a10,f11 p ? io power supply. corevdd a2,c2,l10, j10 p ? core power supply. vss b2,f2,k2, g5,f9,b10, k10 p ? gnd for iovdd and corevdd. epson research and development page 25 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 4.3 summary of configuration options these pins are used for configuration of the s1d13a05 and must be connected directly to iov dd or v ss . the state of cnf[6:0] are latched on the rising edge of reset#. changing state at any other time has no effect. note if cnf5 = 1, the wait# pin should be tied low using a pull-down resistor. if cnf5 = 0, the wait# pin should be tied high using a pull-up resistor. if wait# is not used, this pin should be tied either high or low using a pull-up or pull-down resistor. table 4-7: summary of power-on/reset options s1d13a05 configuration input power-on/reset state 1 (connected to io v dd ) 0 (connected to v ss ) cnf4,cnf[2:0] select host bus interface as follows: cnf4 cnf2 cnf1 cnf0 host bus 1000sh-4/sh-3 interface, big endian 0000sh-4/sh-3 interface, little endian 1001mc68k #1, big endian 0001reserved 1010mc68k #2, big endian 0010reserved 1011generic #1, big endian 0011generic #1, little endian 1100reserved 0100generic #2, little endian 1101redcap2, big endian 0101reserved 1110dragonball (mc68ez328/vz328/sz 328), big endian 0110reserved x111reserved cnf3 reserved. must be set to 1. cnf5 (see note) wait# is active high wait# is active low cnf6 clki to bclk divide ratio 2:1 clki to bclk divide ratio 1:1 page 26 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 4.4 host bus interface pin mapping note 1 a0 for these busses is not used internally by the s1d13a05 and should be connected to v ss . 2 if the target mc68k bus is 32-bit, then these signals should be connected to d[31:16]. table 4-8: host bus interface pin mapping s1d13a05 pin name generic #1 generic #2 hitachi sh-3 /sh-4 motorola mc68k #1 motorola mc68k #2 motorola redcap2 motorola mc68ez328/ mc68vz328 dragonball ab[17:1] a[17:1] a[17:1] a[17:1] a[17:1] a[17:1] a[17:1] a[17:1] ab0 a0 1 a0 a0 1 lds# a0 a0 1 a0 1 db[15:0] d[15:0] d[15:0] d[15:0] d[15:0] d[15:0] 2 d[15:0] d[15:0] cs# external decode csn# external decode csn cs x m/r# external decode clki busclk busclk ckio clk clk clk clko bs# connected to iov dd bs# as# as# connected to iov dd rd/wr# rd1# connected to iov dd rd/wr# r/w# r/w# r/w connected to iov dd rd# rd0# rd# rd# connected to iov dd siz1 oe oe we0# we0# we# we0# connected to iov dd siz0 eb1 lwe we1# we1# bhe# we1# uds# ds# eb0 uwe wait# wait# wait# wait#/ rdy# dtack# dsack1# n/a dtack reset# reset# reset# reset# reset# reset# reset_out reset epson research and development page 27 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 4.5 lcd interface pin mapping note 1 gpio pins which are used by the hr-tft, casio, tft type 2, and tft type 3 interfaces, must be configured as outputs using reg[64h] bits 23-16 after every reset or power-up. 2 these pin mappings use signal names commonly used for each panel type, however signal names may differ between panel manufacturers. the values shown in brackets represent the color components as mapped to the corresponding fpdatxx signals at the first valid edge of fpshift. for further fpdatxx to lcd interface mapping, see section 6.5, ?display interface? on page 52. 3 the s1d13a05 also supports the 9-bit and 12-bit variations of the type 4 tft panel. table 4-9: lcd interface pin mapping pin name monochrome passive panel color passive panel color tft panel usb single single generic tft (tft type 1) sharp hr-tft 1 casio tft 1 tft type 2 1 tft type 3 1 tft type 4 4-bit format 1 8-bit format 2 8-bit 16-bit 4-bit 8-bit 9-bit 12-bit 18-bit 18-bit 18-bit 18-bit 18-bit 18-bit 3 fpframe fpframe sps gsrt stv stv fpframe ? fpline fpline lp gpck stb lp fpline ? fpshift fpshift dclk clk clk cph fpshift ? drdy mod fpshift 2 mod drdy driven 0 no connect inv inv drdy ? fpdat0 driven 0 d0 driven 0 d0 (b5) 2 d0 (g3) 2 d0 (r6) 2 r2 r3 r5 r5 r5 r5 r5 r5 ? fpdat1 driven 0 d1 driven 0 d1 (r5) 2 d1 (r3) 2 d1 (g5) 2 r1 r2 r4 r4 r4 r4 r4 r4 ? fpdat2 driven 0 d2 driven 0 d2 (g4) 2 d2 (b2) 2 d2 (b4) 2 r0 r1 r3 r3 r3 r3 r3 r3 ? fpdat3 driven 0 d3 driven 0 d3 (b3) 2 d3 (g2) 2 d3 (r4) 2 g2 g3 g5 g5 g5 g5 g5 g5 ? fpdat4 d0 d4 d0 (r2) 2 d4 (r3) 2 d4 (r2) 2 d8 (b5) 2 g1 g2 g4 g4 g4 g4 g4 g4 ? fpdat5 d1 d5 d1 (b1) 2 d5 (g2) 2 d5 (b1) 2 d9 (r5) 2 g0 g1 g3 g3 g3 g3 g3 g3 ? fpdat6 d2 d6 d2 (g1) 2 d6 (b1) 2 d6 (g1) 2 d10 (g4) 2 b2 b3 b5 b5 b5 b5 b5 b5 ? fpdat7 d3 d7 d3 (r1) 2 d7 (r1) 2 d7 (r1) 2 d11 (b3) 2 b1 b2 b4 b4 b4 b4 b4 b4 ? fpdat8 driven 0 driven 0 driven 0 driven 0 driven 0 d4 (g3) 2 b0 b1 b3 b3 b3 b3 b3 b3 ? fpdat9 driven 0 driven 0 driven 0 driven 0 driven 0 d5 (b2) 2 driven 0 r0 r2 r2 r2 r2 r2 r2 ? fpdat10 driven 0 driven 0 driven 0 driven 0 driven 0 d6 (r2) 2 driven 0 driven 0 r1 r1 r1 r1 r1 r1 ? fpdat11 driven 0 driven 0 driven 0 driven 0 driven 0 d7 (g1) 2 driven 0 driven 0 r0 r0 r0 r0 r0 r0 ? fpdat12 driven 0 driven 0 driven 0 driven 0 driven 0 d12 (r3) 2 driven 0 g0 g2 g2 g2 g2 g2 g2 ? fpdat13 driven 0 driven 0 driven 0 driven 0 driven 0 d13 (g2) 2 driven 0 driven 0 g1 g1 g1 g1 g1 g1 ? fpdat14 driven 0 driven 0 driven 0 driven 0 driven 0 d14 (b1) 2 driven 0 driven 0 g0 g0 g0 g0 g0 g0 ? fpdat15 driven 0 driven 0 driven 0 driven 0 driven 0 d15 (r1) 2 driven 0 b0 b2 b2 b2 b2 b2 b2 ? fpdat16 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 b1 b1 b1 b1 b1 b1 ? fpdat17 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 b0 b0 b0 b0 b0 b0 ? gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 gpio0 ps pol vclk cpv gpio0 ? gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 gpio1 cls gres ap oe gpio1 ? gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 gpio2 rev frp pol pol gpio2 ? gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 gpio3 spl sth sth eio gpio3 ? gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 gpio4 usbpup gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 gpio5 usbdetect gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 gpio6 usbdm gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 gpio7 usbdp gpo0 gpo0 (general purpose output) ? gpo1 gpo1 vcom gpo1 ? gpo2 gpo2 xoev gpo2 ? gpo3 gpo3 cmd gpo3 ? gpo4 gpo4 pclk1 gpo4 ? gpo5 gpo5 pclk2 gpo5 ? gpo6 gpo6 xresh gpo6 ? gpo7 gpo7 xresv gpo7 ? gpo8 gpo8 xohv gpo8 ? gpo9 gpo9 xstby gpo9 ? gpo10 gpo10 pmde gpo10 ? pwmout pwmout ? page 28 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 5 d.c. characteristics note when applying supply voltages to the s1d13a05, core v dd must be applied to the chip before, or simultaneously with io v dd , or damage to the chip may result. 1. when core v dd is 2.0v 10%, the mclk must be less than or equal to 30mhz (mclk 30mhz) table 5-1: absolute maximum ratings symbol parameter rating units core v dd supply voltage v ss - 0.3 to 3.0 v io v dd supply voltage v ss - 0.3 to 4.0 v v in input voltage v ss - 0.3 to io v dd + 0.5 v v out output voltage v ss - 0.3 to io v dd + 0.5 v t stg storage temperature -65 to 150 c t sol solder temperature/time 260 for 10 sec. max at lead c table 5-2: recommended operating conditions symbol parameter condition min typ max units core v dd supply voltage v ss = 0 v 1.8 (note 1) 2.0 (note 1) 2.2 (note 1) v v ss = 0 v 2.25 2.5 2.75 v io v dd supply voltage v ss = 0 v 3.0 3.3 3.6 v v in input voltage v ss io v dd v v ss core v dd t opr operating temperature -40 25 85 c table 5-3: electrical characteristics for vdd = 3.3v typical symbol parameter condition min typ max units i dds quiescent current quiescent conditions 170 a i iz input leakage current -1 1 a i oz output leakage current -1 1 a v oh high level output voltage vdd = min i oh = -3ma (type 1) -6ma (type 2) v dd - 0.4 v v ol low level output voltage vdd = min i ol = 3ma (type 1) 6ma (type 2) 0.4 v v ih high level input voltage lvttl level, v dd = max 2.0 v v il low level input voltage lvttl level, v dd = min 0.8 v r pd pull down resistance v in = v dd 20 50 120 k c i input pin capacitance 10 pf c o output pin capacitance 10 pf c io bi-directional pin capacitance 10 pf epson research and development page 29 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 6 a.c. characteristics conditions: io v dd = 3.3v 10% t a = -40 c to 85 c t rise and t fall for all inputs must be < 5 nsec (10% ~ 90%) c l = 50pf (bus/mpu interface) c l = 0pf (lcd panel interface) 6.1 clock timing 6.1.1 input clocks figure 6-1: clock input requirements note maximum internal requirements for clocks derived from clki must be considered when determining the frequency of clki. see section 6.1.2, ?internal clocks? on page 31 for internal clock requirements. table 6-1: clock input requirements for clki when clki to bclk divide > 1 symbol parameter min max units f osc input clock frequency (clki) 100 mhz t osc input clock period (clki) 1/f osc ns t pwh input clock pulse width high (clki) 4.5 ns t pwl input clock pulse width low (clki) 4.5 ns t f input clock fall time (10% - 90%) 5 ns t r input clock rise time (10% - 90%) 5 ns t pwl t pwh t f clock input waveform t r t osc v ih v il 10% 90% page 30 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 note maximum internal requirements for clocks derived from clki must be considered when determining the frequency of clki. see section 6.1.2, ?internal clocks? on page 31 for internal clock requirements. note maximum internal requirements for clocks derived from clki2 must be considered when determining the frequency of clki2. see section 6.1.2, ?internal clocks? on page 31 for internal clock requirements. table 6-2: clock input requirements for clki when clki to bclk divide = 1 symbol parameter min max units f osc input clock frequency (clki) 66 mhz t osc input clock period (clki) 1/f osc ns t pwh input clock pulse width high (clki) 3 ns t pwl input clock pulse width low (clki) 3 ns t f input clock fall time (10% - 90%) 5 ns t r input clock rise time (10% - 90%) 5 ns table 6-3: clock input requirements for clki2 symbol parameter min max units f osc input clock frequency (clki2) 66 mhz t osc input clock period (clki2) 1/f osc ns t pwh input clock pulse width high (clki2) 3 ns t pwl input clock pulse width low (clki2) 3 ns t f input clock fall time (10% - 90%) 5 ns t r input clock rise time (10% - 90%) 5 ns epson research and development page 31 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 6.1.2 internal clocks 1. mclk is derived from bclk, therefore when bclk is greater than 50mhz, mclk must be divided using reg[04h] bits 5-4. note for further information on internal clocks, refer to section 7, ?clocks? on page 85. 6.2 reset# timing figure 6-2 s1d13a05 reset# timing table 6-4: internal clock requirements symbol parameter min max units f bclk bus clock frequency 66 mhz f mclk memory clock frequency (see note 1) corevdd = 2.0v 30 mhz corevdd = 2.5v 50 mhz f pclk pixel clock frequency 50 mhz f pwmclk pwm clock frequency 66 mhz table 6-5 s1d13a05 reset# timing symbol parameter min max units t1 active reset pulse width 1? clki t1 reset# page 32 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3 cpu interface timing 6.3.1 generic #1 interface timing figure 6-3: generic #1 interface timing clk a[16:1], m/r# cs# we0#, we1#, rd0#, rd1# wait# d[15:0] (write) d[15:0] (read) t clk t1 t2 t3 t4 t15 t11 t5 t6 t7 t8 t10 t12 t14 t9 valid valid t13 epson research and development page 33 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. because a0 is not used internally, all addresses are seen by the s1d13a05 as even addresses (16-bit word address aligned on even byte addresses). table 6-6: generic #1 interface timing symbol parameter min max unit f clk bus clock frequency 50 mhz t clk bus clock period 1/f clk ns t1 a[16:1], m/r# setup to first clk rising edge where cs# = 0 and either rd0#, rd1# = 0 or we0#, we1# = 0 0ns t2 cs# setup to clk rising edge 0 ns t3 rd0#, rd1#, we0#, we1# setup to clk rising edge 0 ns t4 rd0#, rd1# or we0#, we1# state change to wait# driven low 3 8 ns t5 a[16:1], m/r# and cs# hold from rd0#, rd1#, we0#, we1# rising edge 0ns t6 cs# deasserted to reasserted 0 ns t7 wait# rising edge to rd0#, rd1#, we0#, we1# rising edge 0 ns t8 we0#, we1#, rd0#, rd1# deasserted to reasserted 1 t clk t9 clk rising edge to wait# rising edge 5 14 ns t10 rising edge of either rd0#, rd1# or we0#, we1# to wait# high impedance 5ns t11 d[15:0] setup to 4th rising clk edge after cs#=0 and we0#, we1#=0 1t clk t12 d[15:0] hold from we0#, we1# rising edge (write cycle) 0 ns t13 d[15:0] valid to wait# rising edge (read cycle) 0.5 t clk t14 d[15:0] hold from rd0#, rd1# rising edge (read cycle) 2 ns t15 cycle length 6 t clk table 6-7: generic #1 interface truth table for little endian we0# we1# rd0# rd1# d[15:8] d[7:0] comments 0 0 1 1 valid valid 16-bit write 0 1 1 1 - valid 8-bit write; data on low byte (even byte address 1 ) 1 0 1 1 valid - 8-bit write; data on high byte (odd byte address 1 ) 1 1 0 0 valid valid 16-bit read 1 1 0 1 - valid 8-bit read; data on low byte (even byte address 1 ) 1 1 1 0 valid - 8-bit read; data on high byte (odd byte address 1 ) table 6-8: generic #1 interface truth table for big endian we0# we1# rd0# rd1# d[15:8] d[7:0] comments 0 0 1 1 valid valid 16-bit write 0 1 1 1 - valid 8-bit write; data on low byte (odd byte address 1 ) 1 0 1 1 valid - 8-bit write; data on high byte (even byte address 1 ) 1 1 0 0 valid valid 16-bit read 1 1 0 1 - valid 8-bit read; data on low byte (odd byte address 1 ) 1 1 1 0 valid - 8-bit read; data on high byte (even byte address 1 ) page 34 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.2 generic #2 interface timing figure 6-4: generic #2 interface timing busclk a[16:0], m/r#, bhe# cs# we#, rd# wait# d[15:0] (write) d[15:0] (read) t busclk t1 t2 t3 t4 t15 t11 t5 t6 t7 t8 t10 t12 t14 t9 valid valid t13 epson research and development page 35 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 table 6-9: generic #2 interface timing symbol parameter min max unit f busclk bus clock frequency 50 mhz t busclk bus clock period 1/f busclk ns t1 a[16:0], m/r#, bhe# setup to first busclk rising edge where cs# = 0 and either rd# = 0 or we# = 0 0ns t2 cs# setup to busclk rising edge 0 ns t3 rd#, we# setup to busclk rising edge 0 ns t4 rd# or we# state change to wait# driven low 3 9 ns t5 a[16:0], m/r#, bhe# and cs# hold from rd#, we# rising edge 0 ns t6 cs# deasserted to reasserted 0 ns t7 wait# rising edge to rd#, we# rising edge 0 ns t8 we#, rd# deasserted to reasserted 1 t busclk t9 wait# rising edge after busclk rising edge 5 14 ns t10 rising edge of either rd# or we# to wait# high impedance 7 ns t11 d[15:0] setup to 4th rising busclk edge after cs#=0 and we#=0 1 t busclk t12 d[15:0] hold from we# rising edge (write cycle) 0 ns t13 d[15:0] valid to wait# rising edge setup (read cycle) 0.5 t busclk t14 d[15:0] hold from rd# rising edge (read cycle) 2 ns t15 cycle length 6 t busclk table 6-10: generic #2 interface truth table for little endian we# rd# bhe# a0 d[15:8] d[7:0] comments 0 1 0 0 valid valid 16-bit write 0 1 1 0 - valid 8-bit write at even address 0 1 0 1 valid - 8-bit write at odd address 1 0 0 0 valid valid 16-bit read 1 0 1 0 - valid 8-bit read at even address 1 0 0 1 valid - 8-bit read at odd address page 36 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.3 hitachi sh-3 interface timing figure 6-5: hitachi sh-3 interface timing note a minimum of one software wait state is required. t ckio t1 t2 t3 t4 t6 t7 t5 t11 t14 t15 t16 t13 t10 t8 t17 t9 ckio a[16:1], m/r#, rd/wr# bs# csn# wen#, rd# wait# d[15:0] (write) d[15:0] (read) t12 epson research and development page 37 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. the s1d13a05 requires 2ns of write data hold time. table 6-11: hitachi sh-3 interface timing symbol parameter min max unit f ckio bus clock frequency 66 mhz t ckio bus clock period 1/f ckio ns t1 a[16:1], rd/wr# setup to ckio 0 ns t2 bs# setup 0 ns t3 bs# hold 9 ns t4 csn# setup 0 ns t5 wen#, rd# setup to next ckio after bs# low 0 ns t6 falling edge csn# to wait# driven low 4 9 ns t7 d[15:0] setup to 3rd ckio rising edge after bs# deasserted (write cycle) 1ns t8 we#, rd# deasserted to a[16:1], m/r#, rd/wr# deasserted 0 ns t9 rising edge of wait# to bs# falling t ckio + 16 ns t10 ckio rising edge before wait# deasserted to wen#, rd# asserted for next cycle 2t ckio t11 rising edge of wait# to we#, rd# deasserted 0 ns t12 wait# rising edge after ckio rising edge 5 14 ns t13 rising edge of csn# to wait# high impedance 6 ns t14 d[15:0] hold from wen# deasserted (write cycle) 0 ns t15 d[15:0] setup to wait# rising edge (read cycle) 0.5 t ckio t16 rising edge of rd# to d[15:0] high impedance (read cycle) 3 7 ns t17 cycle length 5 t ckio page 38 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.4 hitachi sh-4 interface timing figure 6-6: hitachi sh-4 interface timing note a minimum of one software wait state is required. t ckio t1 t2 t3 t4 t6 t7 t5 t11 t15 t16 t17 t13 t10 t8 t18 t9 t14 ckio a[16:1], rd/wr#, m/r# bs# csn# wen#, rd# rdy d[15:0] (write) d[15:0] (read) t12 epson research and development page 39 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 table 6-12: hitachi sh-4 interface timing symbol parameter min max unit f ckio bus clock frequency 66 mhz t ckio bus clock period 1/f ckio ns t1 a[16:1], m/r#, rd/wr# setup to ckio 0 ns t2 bs# setup 0 ns t3 bs# hold 9 ns t4 csn# setup 0 ns t5 wen#, rd# setup to 1st ckio rising edge after bs# low 0 ns t6 falling edge csn# to rdy driven high 3 7 ns t7 d[15:0] setup to 3rd ckio rising edge after bs# deasserted (write cycle) 1ns t8 we#,rd# deasserted to a[16:1],m/r#,rd/wr# deasserted 0 ns t9 rdy falling edge to bs# falling t ckio + 11 ns t10 ckio rising edge before rdy deasserted to wen#, rd# asserted for next cycle 2t ckio t11 rdy falling edge to we#,rd# deasserted 0 ns t12 rdy falling edge after ckio rising edge 5 14 ns t13 rising edge csn# to rdy rising edge 4 10 ns t14 ckio falling edge to rdy tristate 4 12 ns t15 d[15:0] hold from wen# deasserted (write cycle) 0 ns t16 d[15:0] valid setup to rdy falling edge (read cycle) 0.5 t ckio t17 rising edge of rd# to d[15:0] high impedance (read cycle) 2 7 ns t18 cycle length 4 t ckio page 40 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.5 motorola mc68k #1 interface timing figure 6-7: motorola mc68k #1 interface timing t clk t1 t1 t1 t1 t2 t9 t5 t8 t7 t10 t12 t3 t3 t13 t11 t6 clk a[16:1], r/w#, m/r# cs# as# uds#, lds#, (a0) dtack# d[15:0] (write) d[15:0] (read) t4 epson research and development page 41 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 table 6-13: motorola mc68k#1 interface timing symbol parameter min max unit f clk bus clock frequency 50 mhz t clk bus clock period 1/f clk ns t1 a[16:1], m/r#, r/w# and cs# and as# and uds#, lds# setup to first clk rising edge 1ns t2 cs# and as# asserted to dtack# driven 2 7 ns t3 a[16:1], m/r#, r/w# and cs# hold from as# rising edge 0 ns t4 as# rising edge to clk falling edge 1 ns t5 dtack# falling edge to uds#, lds# rising edge 0 ns t6 clk rising edge to dtack# falling edge 5 14 ns t7 as# rising edge to dtack# rising edge 3 9 ns t8 1st clk falling edge after as# deasserted to dtack# high impedance 0.5 t clk + 12 ns t9 d[15:0] valid to 4th clk rising edge where cs# = 0, as# = 0 and either uds# = 0 or lds# = 0 (write cycle) 1t clk t10 d[15:0] hold from dtack# falling edge (write cycle) 0 ns t11 d[15:0] valid setup time to dtack# goes low (read cycle) 0.5 t clk t12 uds#, lds# rising edge to d[15:0] high impedance (read cycle) 2 ns t13 cycle length 7 t clk page 42 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.6 motorola mc68k #2 interface timing figure 6-8: motorola mc68k #2 interface timing t3 t4 t clk t1 t1 t1 t1 t2 t13 t14 t11 t12 t9 t10 t7 t15 t5 t6 valid valid clk a[16:1], m/r#, r/w#, siz[1:0] cs# as# ds# dsack1# d[31:16] (write) d[31:16] (read) t8 epson research and development page 43 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 table 6-14: motorola mc68k#2 interface timing symbol parameter min max unit f clk bus clock frequency 50 mhz t clk bus clock period 1/f clk ns t1 a[16:0], m/r#, r/w#, siz[1:0] and cs# and as# and ds# setup to first clk rising edge 0ns t2 cs# and as# asserted low to dsack1# driven 2 7 ns t3 a[16:1], m/r#, r/w#, siz[1:0] hold from as# rising edge 0 ns t4 cs# hold from as# rising edge 0 ns t5 ds# rising edge to as# rising edge 0 ns t6 as# setup to clk falling edge 1 ns t7 dsack1# falling edge to ds# rising edge 0 ns t8 clk rising edge to dsack1# falling edge 5 14 ns t9 as# rising edge to dsack1# rising edge 3 9 ns t10 1st clk falling edge after as# deasserted to dsack1# high impedance t clk + 3 ns t11 d[15:0] setup to 4th clk rising edge after cs#=0, as#=0, ds#=0, and dsack1#=0 1t clk t12 d[15:0] hold from dsack1# falling edge 0 ns t13 d[15:0] valid setup to dsack1# falling edge (read cycle) 0.5 t clk t14 ds# rising edge to d[15:0] high impedance (read cycle) 2 9 ns t15 cycle length 7 t clk page 44 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.7 motorola redcap2 interface timing figure 6-9: motorola redcap2 interface timing cko a[16:1], r/w#, cs# ebo#, eb1# (write) d[15:0] (write) eb0#, eb1#, oe# (read) d[15:0] (read) t cko t1 t2 t5 t7 t6 t3 t4 t11 t10 t9 t12 t8 valid valid epson research and development page 45 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. the cycle length for the redcap interface is fixed at 10 t cko . 2. the read and write 2d bitblt functions are not available when using the redcap interface. table 6-15: motorola redcap2 interface timing symbol parameter min max unit f cko bus clock frequency 17 mhz t cko bus clock period 1/f cko ns t1 a[16:1], r/w, csn# setup to cko rising edge 0 ns t2 eb0 ,eb1 setup to cko rising edge (write) 0 ns t3 d[15:0] input setup to 4th cko rising edge after csn# and eb0 or eb1 asserted low (write cycle) 1t cko t4 d[15:0] input hold from 4th cko rising edge after csn# and eb0 or eb1 asserted low (write cycle) 7ns t5 eb0 ,eb1 ,oe setup to cko rising edge (read cycle) 0 ns t6a 1st cko rising edge after csn#, eb0 or eb1,oe asserted low to d[15:0] valid for mclk = bclk (read cycle) 6t cko +17 ns t6b 1st cko rising edge after csn#, eb0 or eb1,oe asserted low to d[15:0] valid for mclk = bclk 2 (read cycle) 9t cko +17 ns t6c 1st cko rising edge after csn#, eb0 or eb1,oe asserted low to d[15:0] valid for mclk = bclk 3 (read cycle) 12t cko +17 ns t6d 1st cko rising edge after csn#, eb0 or eb1,oe asserted low to d[15:0] valid for mclk = bclk 4 (read cycle) 15t cko +17 ns t7 eb0 ,eb1 ,oe falling edge to d[15:0] driven (read cycle) 2 9 ns t8 a[16:1], r/w, csn hold from cko rising edge 0 ns t9 eb0, eb1 setup to cko rising edge (write cycle) 1 ns t10 cko falling edge to eb0, eb1, oe deasserted (read) 0 ns t11 oe, eb0, eb1 deasserted to d[15:0] output high impedance (read) 2 8 ns t12 cycle length (note 1) t cko page 46 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.8 motorola dragonball interface timing with dtac k figure 6-10: motorola dragonball interface timing with dtac k clko a[16:1] csx# uwe#, lwe# (write) oe# (read) d[15:0] (write) d[15:0] (read) dtack# t clko t1 t3 t4 t13 t4 t5 t7 t9 t12 t11 t8 t6 t2 valid valid t1 t1 t1 t10 epson research and development page 47 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. the mc68sz328 with a maximum clock frequency of 66mhz is supported. the mc68vz328 with a maximum clock frequency of 33mhz is supported. the mc68ez328 with a maximum clock frequency of 16mhz is supported. table 6-16: motorola dragonball interface timing with dtack symbol parameter min max unit f clko clock frequency 66 (note 1) mhz t clko clock period 1/f clko ns t1 a[16:1], csx , uwe , lwe , oe setup to clko rising edge 1ns t2 csx asserted low to dtack driven 27ns t3 a[16:1] hold from csx rising edge 0ns t4 dtack falling edge to uwe , lwe and csx rising edge 0ns t5 uwe , lwe deasserted to reasserted 1t clko t6 d[15:0] valid to fourth clko rising edge where csx = 0 and uwe = 0 or lwe = 0 (write cycle) 1t clko t7 d[15:0] hold from dtack falling edge (write cycle) 0ns t8 d[15:0] valid setup to dtack falling edge (read cycle) 0.5 t clko t9 csx rising edge to d[15:0] high impedance (read cycle) 26ns t10 clko rising edge to dtack# falling edge 5 14 ns t11 csx rising edge to dtack rising edge 39ns t12 first clko falling edge after deassertion of csx# to dtack# high impedance 0.5t clko + 4 0.5t clko + 8 ns t13 cycle length 8 t clko page 48 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.3.9 motorola dragonball interface timing w/o dtack figure 6-11: motorola dragonball interface timing w/o dtac k t clko t1 t2 t3 t4 t7 t5 t6 t5 t5 t5 clko a[16:1] csx# uwe#, lwe# (write) oe# d[15:0] (write) d[15:0] (read) t1 t1 t1 epson research and development page 49 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. the mc68vz328 with a maximum clock frequency of 33mhz is supported. the mc68ez328 with a maximum clock frequency of 16mhz is supported. 2. the mc68ez328 does not support the mclk = bclk 3 and mclk = bclk 4 options. the mc68vz328 does not support the mclk = bclk 4 option. 3. the cycle length for the dragonball w/o dtack interface is fixed at 10 t clko . 4. the read and write 2d bitblt functions are not available when using the dragonball w/o dtack interface. table 6-17: motorola dragonball interface timing w/o dtack symbol parameter min max unit f clko bus clock frequency 33 (note 1) mhz t clko bus clock period 1/f clko ns t1 a[16:1] and csx# and uwe#, lwe# and oe# setup to clko rising edge 1ns t2 d[15:0] valid to 4th clk rising edge where csx# = 0 and uwe# = 0 or lwe# = 0 (write cycle) 1t clko t3 csx# and oe# asserted low to d[15:0] driven (read cycle) 2 8 ns t4a 1st clko rising edge after csx# and oe# asserted to d[15:0] valid for mclk=bclk (read cycle) 7t clko t4b 1st clko rising edge after csx# and oe# asserted to d[15:0] valid for mclk=bclk 2 (read cycle) 10 t clko t4c 1st clko rising edge after csx# and oe# asserted to d[15:0] valid for mclk=bclk 3 (read cycle) (see note 2) 13 t clko t5 a[16:1] and uwe#, lwe# and oe# and d[15:0] (write) hold from csx# rising edge 0ns t6 csx# rising edge to d[15:0] high impedance 2 8 ns t7 cycle length (see note 3) t clko page 50 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.4 lcd power sequencing 6.4.1 passive/tft power-on sequence figure 6-12: passive/tft power-on sequence timing 1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected. table 6-18: passive/tft power-on sequence timing symbol parameter min max units t1 lcd signals active to lcd bias active note 1 note 1 t2 power save mode disabled to lcd signals active 01bclk *it is recommended to use the general purpose io pin gpio0 to control the lcd bias power. **the lcd power-on sequence is activated by programming the power save mode enable bit (reg[14h] bit 4) to 0. ***lcd signals include: fpdat[17:0], fpshift, fpline, fpframe, and drdy. gpio0* power save mode enable** lcd signals*** (reg[14h] bit 4) t2 t1 epson research and development page 51 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 6.4.2 passive/tft power-off sequence figure 6-13: passive/tft power-off sequence timing 1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected. table 6-19: passive/tft power-off sequence timing symbol parameter min max units t1 lcd bias deactivated to lcd signals inactive note 1 note 1 t2 power save mode enabled to lcd signals low 01bclk *it is recommended to use the general purpose io pin gpio0 to control the lcd bias power. **the lcd power-off sequence is activated by programming the power save mode enable bit (reg[14h] bit 4) to 1. ***lcd signals include: fpdat[17:0], fpshift, fpline, fpframe, and drdy. gpio0* power save mode enable** lcd signals*** (reg[14h] bit 4) t2 t1 page 52 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5 display interface the timing parameters required to drive a flat panel display are shown below. timing details for each supported panel type are provided in the remainder of this section. figure 6-14: panel timing parameters 1. for passive panels, the hdp must be a minimum of 32 pixels and must be increased by multiples of 16. for tft panels, the hdp must be a minimum of 8 pixels and must be increased by multiples of 8. 2. the following formulas must be valid for all panel timings: hdps + hdp < ht vdps + vdp < vt table 6-20: panel timing parameter definition and register summary symbol description derived from units ht horizontal total ((reg[20h] bits 6-0) + 1) x 8 ts hdp 1 horizontal display period 1 ((reg[24h] bits 6-0) + 1) x 8 hdps horizontal display period start position for stn panels: ((reg[28h] bits 9-0) + 22 ) for tft panels: ((reg[28h] bits 9-0) + 5 ) hps fpline pulse start position (reg[2ch] bits 9-0) + 1 hpw fpline pulse width (reg[2ch] bits 22-16) + 1 vt vertical total (reg[30h] bits 9-0) + 1 lines (ht) vdp vertical display period (reg[34h] bits 9-0) + 1 vdps vertical display period start position reg[38h] bits 9-0 vps fpframe pulse start position reg[3ch] bits 9-0 vpw fpframe pulse width (reg[3ch] bits 18-16) + 1 ht vdp vt vdps vpw vps hdp hpw hps hdps epson research and development page 53 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 6.5.1 generic stn panel timing figure 6-15: generic stn panel timing vt = vertical total = [(reg[30h] bits 9-0) + 1] lines vps = fpframe pulse start position = 0 lines, because reg[3ch] bits 9-0 = 0 vpw = fpframe pulse width = [(reg[3ch] bits 18-16) + 1] lines vdps = vertical display period start position = 0 lines, because reg[38h] bits 9-0 = 0 vdp = vertical display period = [(reg[34h] bits 9-0) + 1] lines ht = horizontal total = [((reg[20h] bits 6-0) + 1) x 8] pixels hps = fpline pulse start position = [(reg[2ch] bits 9-0) + 1] pixels hpw = fpline pulse width = [(reg[2ch] bits 22-16) + 1] pixels hdps = horizontal display period start position= 22 pixels, because reg[28h] bits 9-0 = 0 hdp = horizontal display period = [((reg[24h] bits 6-0) + 1) x 8] pixels *for passive panels, the hdp must be a minimum of 32 pixels and must be increased by multiples of 16. *hps should comply with the following formula: hps > hdp + 22 hps + hpw < ht *panel type bits (reg[0ch] bits 1-0) = 00b (stn) *fpframe pulse polarity bit (reg[3ch] bit 23) = 1 (active high) *fpline polarity bit (reg[2ch] bit 23) = 1 (active high) *mod 1 is the mod signal when reg[0ch] bits 21-16 = 0 (mod toggles every fpframe) *mod 2 is the mod signal when reg[0ch] bits 21-16 = n (mod toggles every n fpline) fpframe fpline mod 1 (drdy) fpdat[17:0] fpline fpshift mod 2 (drdy) fpdat[17:0] vt (= 1 frame) vpw vdp hpw ht (= 1 line) hps hdps hdp 1 pclk page 54 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.2 single monochrome 4-bit panel timing figure 6-16: single monochrome 4-bit panel timing vdp = vertical display period = (reg[34h] bits 9:0) + 1 lines vndp = vertical non-display period = vt - vdp = (reg[30h] bits 9:0) - (reg[34h] bits 9:0) lines hdp = horizontal display period = ((reg[24h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[20h] bits 6:0) + 1) x 8ts) - (((reg[24h] bits 6:0) + 1) x 8ts) fpline fpshift fpframe fpline drdy (mod) drdy (mod) * diagram drawn with 2 fpline vertical blank period example timing for a 320x240 panel fpdat[7:4] fpdat6 fpdat5 fpdat4 fpdat7 vdp line1 line2 line3 line4 line239 line240 line1 line2 1-2 1-6 1-318 1-3 1-7 1-319 1-4 1-8 1-320 1-1 1-5 1-317 vndp hdp hndp invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid epson research and development page 55 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 6-17: single monochrome 4-bit panel a.c. timing 1. ts = pixel clock period 2. t1 min = hps + t4 min 3. t2 min = t3 min - (hps + t4 min ) 4. t3 min = ht 5. t4 min = hpw 6. t5 min = hps - 1 7. t6 min = hps - (hdp + hdps) + 2, if negative add t3 min 8. t14 min = hdps - (hps + t4 min ), if negative add t3 min table 6-21: single monochrome 4-bit panel a.c. timing symbol parameter min typ max units t1 fpframe setup to fpline falling edge note 2 ts (note 1) t2 fpframe hold from fpline falling edge note 3 ts t3 fpline period note 4 ts t4 fpline pulse width note 5 ts t5 mod transition to fpline rising edge note 6 ts t6 fpshift falling edge to fpline rising edge note 7 ts t7 fpshift falling edge to fpline falling edge t6 + t4 ts t8 fpline falling edge to fpshift falling edge t14 + 2 ts t9 fpshift period 4 ts t10 fpshift pulse width low 2 ts t11 fpshift pulse width high 2 ts t12 fpdat[7:4] setup to fpshift falling edge 1 ts t13 fpdat[7:4] hold to fpshift falling edge 2 ts t14 fpline falling edge to fpshift rising edge note 8 ts fpframe fpline drdy (mod) sync timing fpline fpshift fpdat[7:4] data timing t12 t13 t14 t10 t11 t5 t1 t2 t3 t4 t8 t9 12 t7 t6 page 56 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.3 single monochrome 8-bit panel timing figure 6-18: single monochrome 8-bit panel timing vdp = vertical display period = (reg[34h] bits 9:0) + 1 lines vndp = vertical non-display period = vt - vdp = (reg[30h] bits 9:0) - (reg[34h] bits 9:0) lines hdp = horizontal display period = ((reg[24h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[20h] bits 6:0) + 1) x 8ts) - (((reg[24h] bits 6:0) + 1) x 8ts) fpline fpshift fpframe fpline drdy (mod) drdy (mod) * diagram drawn with 2 fpline vertical blank period example timing for a 640x480 panel fpdat[7:0] fpdat6 fpdat5 fpdat4 fpdat7 fpdat2 fpdat1 fpdat0 fpdat3 hndp vdp line1 line2 line3 line4 line479 line480 line1 line2 1-2 1-10 1-634 1-3 1-11 1-635 1-4 1-12 1-636 1-5 1-13 1-637 1-6 1-14 1-638 1-7 1-15 1-639 1-8 1-16 1-640 1-1 1-9 1-633 vndp hdp invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid epson research and development page 57 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 6-19: single monochrome 8-bit panel a.c. timing 1. ts = pixel clock period 2. t1 min = hps + t4 min 3. t2 min = t3 min - (hps + t4 min ) 4. t3 min = ht 5. t4 min = hpw 6. t5 min = hps - 1 7. t6 min = hps - (hdp + hdps) + 4, if negative add t3 min 8. t14 min = hdps - (hps + t4 min ), if negative add t3 min table 6-22: single monochrome 8-bit panel a.c. timing symbol parameter min typ max units t1 fpframe setup to fpline falling edge note 2 ts (note 1) t2 fpframe hold from fpline falling edge note 3 ts t3 fpline period note 4 ts t4 fpline pulse width note 5 ts t5 mod transition to fpline rising edge note 6 ts t6 fpshift falling edge to fpline rising edge note 7 ts t7 fpshift falling edge to fpline falling edge t6 + t4 ts t8 fpline falling edge to fpshift falling edge t14 + 4 ts t9 fpshift period 8 ts t10 fpshift pulse width low 4 ts t11 fpshift pulse width high 4 ts t12 fpdat[7:0] setup to fpshift falling edge 4 ts t13 fpdat[7:0] hold to fpshift falling edge 4 ts t14 fpline falling edge to fpshift rising edge note 8 ts t12 t13 fpframe fpline drdy (mod) sync timing fpline fpshift fpdat[7:0] data timing t5 t1 t2 t3 t4 t14 t8 t9 t10 t11 12 t7 t6 page 58 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.4 single color 4-bit panel timing figure 6-20: single color 4-bit panel timing vdp = vertical display period = (reg[34h] bits 9:0) + 1 lines vndp = vertical non-display period = vt - vdp = (reg[30h] bits 9:0) - (reg[34h] bits 9:0) lines hdp = horizontal display period = ((reg[24h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[20h] bits 6:0) + 1) x 8ts) - (((reg[24h] bits 6:0) + 1) x 8ts) fpline fpframe fpline drdy (mod) drdy (mod) fpshift vdp line1 line2 line3 line4 line239 line240 line1 line2 vndp 1-r1 1-g1 1-b1 1-r2 1-g2 1-b2 1-r3 1-g3 1-b3 1-r4 1-g4 1-b4 1-b319 1-r320 1-g320 1-b320 hdp hndp fpdat[7:4] fpdat4 fpdat5 fpdat6 fpdat7 invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid - diagram drawn with 2 fpline vertical blank period - example timing for a 320x240 panel notes: - ts = pixel clock period (pclk) - fpshift uses extended low states in order to process 8 pixels in 6 fpshift clocks .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts .5ts 2.5ts .5ts .5ts .5ts epson research and development page 59 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 6-21: single color 4-bit panel a.c. timing 1. ts = pixel clock period 2. t1 min = hps + t4 min 3. t2 min = t3 min - (hps + t4 min ) 4. t3 min = ht 5. t4 min = hpw 6. t5 min = hps - 1 7. t6 min = hps - (hdp + hdps) + 1.5), if negative add t3 min 8. t14 min = hdps - (hps + t4 min ) + 1, if negative add t3 min table 6-23: single color 4-bit panel a.c. timing symbol parameter min typ max units t1 fpframe setup to fpline falling edge note 2 ts (note 1) t2 fpframe hold from fpline falling edge note 3 ts t3 fpline period note 4 ts t4 fpline pulse width note 5 ts t5 mod transition to fpline rising edge note 6 ts t6 fpshift falling edge to fpline rising edge note 7 ts t7 fpshift falling edge to fpline falling edge t6 + t4 ts t8 fpline falling edge to fpshift falling edge t14 + 0.5 ts t9 fpshift period 1 ts t10 fpshift pulse width low 0.5 ts t11 fpshift pulse width high 0.5 ts t12 fpdat[7:4] setup to fpshift falling edge 0.5 ts t13 fpdat[7:4] hold to fpshift falling edge 0.5 ts t14 fpline falling edge to fpshift rising edge note 8 ts fpframe fpline drdy (mod) sync timing fpline fpshift fpdat[7:4] data timing t14 t1 t2 t3 t4 t8 t9 t10 t11 t12 t13 12 t7 t6 t5 page 60 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.5 single color 8-bit panel timing (format 1) figure 6-22: single color 8-bit panel timing (format 1) vdp = vertical display period = (reg[34h] bits 9:0) + 1 lines vndp = vertical non-display period = vt - vdp = (reg[30h] bits 9:0) - (reg[34h] bits 9:0) lines hdp = horizontal display period = ((reg[24h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[20h] bits 6:0) + 1) x 8ts) - (((reg[24h] bits 6:0) + 1) x 8ts) fpline fpshift2 fpframe fpline fpshift fpdat[7:0] vdp line1 line2 line3 line4 line239 line240 line1 line2 hdp vndp hndp fpdat5 fpdat6 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 fpdat7 invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid - diagram drawn with 2 fpline vertical blank period - example timing for a 320x240 panel notes: - ts = pixel clock period (pclk) - the duty cycle of fpshift changes in order to process 16 pixels in 6 fpshift/fpshift2 rising edges 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 4ts 4ts 4ts 4ts 4ts 4ts 4ts 4ts 2ts 2ts 2ts 2ts 2ts 2ts 2ts 1-r1 1-b1 1-g2 1-r3 1-b3 1-g4 1-r5 1-b5 1-r6 1-g5 1-b4 1-r4 1-r9 1-g9 1-g14 1-b14 1-r14 1-g13 1-b12 1-r12 1-b6 1-g6 1-r7 1-b7 1-g8 1-b9 1-g10 1-r11 1-g11 1-b16 1-b10 1-r10 1-b8 1-r8 1-g7 1-b11 1-b2 1-r2 1-g1 1-g3 1-r15 1-b15 1-g16 1-b13 1-g15 1-r13 1-g12 1-r16 1- r316 1- r316 1- b316 1- g317 1- r318 1- b318 1- g319 1- r320 1- b320 epson research and development page 61 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 6-23: single color 8-bit panel a.c. timing (format 1) 1. ts = pixel clock period 2. t1 min = hps + t4 min 3. t2 min = t3 min - (hps + t4 min ) 4. t3 min = ht 5. t4 min = hpw 6. t6a min = hps - (hdp + hdps), if negative add t3 min 7. t6b min = hps - (hdp + hdps) + 2, if negative add t3 min 8. t14 min = hdps - (hps + t4 min ), if negative add t3 min table 6-24: single color 8-bit panel a.c. timing (format 1) symbol parameter min typ max units t1 fpframe setup to fpline falling edge note 2 ts (note 1) t2 fpframe hold from fpline falling edge note 3 ts t3 fpline period note 4 ts t4 fpline pulse width note 5 ts t6a fpshift falling edge to fpline rising edge note 6 ts t6b fpshift2 falling edge to fpline rising edge note 7 ts t7a fpshift falling edge to fpline falling edge t6a + t4 ts t7b fpshift2 falling edge to fpline falling edge t6b + t4 ts t8 fpline falling edge to fpshift rising, fpshift2 falling edge t14 + 2 ts t9 fpshift2, fpshift period 4 6 ts t10 fpshift2, fpshift pulse width low 2 ts t11 fpshift2, fpshift pulse width high 2 ts t12 fpdat[7:0] setup to fpshift2, fpshift falling edge 1 ts t13 fpdat[7:0] hold from fpshift2, fpshift falling edge 1 ts t14 fpline falling edge to fpshift rising edge note 8 ts fpframe fpline sync timing fpline fpshift fpdat[7:0] data timing t14 t1 t2 t3 t4 t8 t9 t10 t11 t12 t13 2 1 t7a t6b fpshift2 t6a t7b t12 t13 page 62 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.6 single color 8-bit panel timing (format 2) figure 6-24: single color 8-bit panel timing (format 2) vdp = vertical display period = (reg[34h] bits 9:0) + 1 lines vndp = vertical non-display period = vt - vdp = (reg[30h] bits 9:0) - (reg[34h] bits 9:0) lines hdp = horizontal display period = ((reg[24h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[20h] bits 6:0) + 1) x 8ts) - (((reg[24h] bits 6:0) + 1) x 8ts) fpline fpframe fpline drdy (mod) drdy (mod) fpshift vdp line1 line2 line3 line4 line239 line240 line1 line2 vndp 1-r1 1-g1 1-b1 1-r2 1-g2 1-b 2 1-r3 1-g3 1-b3 1-r4 1-g4 1-b4 1-r5 1-g5 1-b5 1-r6 1-g6 1-b6 1-r7 1-g7 1-b7 1-r8 1-g8 1-b8 1-g318 1-b318 1-r319 1-g319 1-b319 1-r320 1-g320 1-b320 hdp hndp fpdat[7:0] fpdat7 fpdat6 fpdat5 fpdat4 fpdat3 fpdat2 fpdat1 fpdat0 invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid 2ts 2ts 2ts 2ts 2ts 2ts ts ts ts ts ts ts ts ts ts ts ts - diagram drawn with 2 fpline vertical blank period - example timing for a 320x240 panel notes: - ts = pixel clock period (pclk) - the duty cycle of fpshift changes in order to process 8 pixels in 3 fpshift rising clocks epson research and development page 63 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 6-25: single color 8-bit panel a.c. timing (format 2) 1. ts = pixel clock period 2. t1 min = hps + t4 min 3. t2 min = t3 min - (hps + t4 min ) 4. t3 min = ht 5. t4 min = hpw 6. t5 min = hps - 1 7. t6 min = hps - (hdp + hdps) + 1, if negative add t3 min 8. t14 min = hdps - (hps + t4 min ), if negative add t3 min table 6-25: single color 8-bit panel a.c. timing (format 2) symbol parameter min typ max units t1 fpframe setup to fpline falling edge note 2 ts (note 1) t2 fpframe hold from fpline falling edge note 3 ts t3 fpline period note 4 ts t4 fpline pulse width note 5 ts t5 mod transition to fpline rising edge note 6 ts t6 fpshift falling edge to fpline rising edge note 7 ts t7 fpshift falling edge to fpline falling edge t6 + t4 ts t8 fpline falling edge to fpshift falling edge t14 + 2 ts t9 fpshift period 2 ts t10 fpshift pulse width low 1 ts t11 fpshift pulse width high 1 ts t12 fpdat[7:0] setup to fpshift falling edge 1 ts t13 fpdat[7:0] hold to fpshift falling edge 1 ts t14 fpline falling edge to fpshift rising edge note 8 ts t14 t10 t11 t12 t13 data timing fpframe t1 t2 t3 t5 t4 fpline drdy (mod) sync timing fpline fpshift t8 t9 12 t7 t6 fpdat[7:0] page 64 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.7 single color 16-bit panel timing figure 6-26: single color 16-bit panel timing vdp = vertical display period = (reg[34h] bits 9:0) + 1 lines vndp = vertical non-display period = vt - vdp = (reg[30h] bits 9:0) - (reg[34h] bits 9:0) lines hdp = horizontal display period = ((reg[24h] bits 6:0) + 1) x 8ts hndp = horizontal non-display period = ht - hdp = (((reg[20h] bits 6:0) + 1) x 8ts) - (((reg[24h] bits 6:0) + 1) x 8ts) vdp fpline fpshift line1 line2 line3 line4 line479 line480 fpframe line1 line2 fpline drdy (mod) drdy (mod) vndp hdp 1-r1 1-g6 1-g635 1-b1 1-r7 1-g636 1-g2 1-b7 1-r637 1-r3 1-g8 1-b637 1-b3 1-r9 1-g638 1-g4 1-b9 1-r639 1-r5 1-g10 1-b639 1-g1 1-b6 1-r636 1-r2 1-g7 1-b636 1-b2 1-r8 1-g637 1-g3 1-b8 1-r638 1-r4 1-g9 1-b638 1-b4 1-r10 1-g639 1-g5 1-b10 1-r640 1-r6 1-g11 1-b640 1-b11 1-g12 1-r13 1-b13 1-g14 1-r15 1-b15 1-r12 1-b12 1-g13 1-r14 1-b14 1-g15 1-r16 1-b16 1-b5 1-r11 1-g640 1-g16 hndp - diagram drawn with 2 fpline vertical blank period - example timing for a 640x480 panel fpdat[15:0] fpdat15 fpdat9 fpdat8 fpdat3 fpdat2 fpdat1 fpdat0 fpdat5 fpdat4 fpdat11 fpdat10 fpdat12 fpdat7 fpdat6 fpdat13 fpdat14 invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid invalid - 3ts 3ts 3ts 3ts 3ts 3ts 3ts 3ts 3ts 2ts 2ts 2ts 2ts 3ts 3ts 3ts 2ts 3ts 3ts 2ts notes: - ts = pixel clock period (pclk) - the duty cycle of fpshift changes in order to process 16 pixels in 3 fpshift rising clocks epson research and development page 65 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 6-27: single color 16-bit panel a.c. timing 1. ts = pixel clock period 2. t1 min = hps + t4 min 3. t2 min = t3 min - (hps + t4 min ) 4. t3 min = ht 5. t4 min = hpw 6. t5 min = hps - 1 7. t6 min = hps - (hdp + hdps) + 2, if negative add t3 min 8. t14 min = hdps - (hps + t4 min ), if negative add t3 min table 6-26: single color 16-bit panel a.c. timing symbol parameter min typ max units t1 fpframe setup to fpline falling edge note 2 ts (note 1) t2 fpframe hold from fpline falling edge note 3 ts t3 fpline period note 4 ts t4 fpline pulse width note 5 ts t5 mod transition to fpline rising edge note 6 ts t6 fpshift falling edge to fpline rising edge note 7 ts t7 fpshift falling edge to fpline falling edge t6 + t4 ts t8 fpline falling edge to fpshift falling edge t14 + 3 ts t9 fpshift period 5 ts t10 fpshift pulse width low 2 ts t11 fpshift pulse width high 2 ts t12 fpdat[15:0] setup to fpshift rising edge 2 ts t13 fpdat[15:0] hold to fpshift rising edge 2 ts t14 fpline falling edge to fpshift rising edge note 8 ts t14 t10 t11 data timing fpframe t1 t2 t3 t5 t4 fpline drdy (mod) sync timing fpline fpshift t8 t9 t7 t6 t12 t13 12 fpdat[15:0] page 66 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.8 generic tft panel timing figure 6-28: generic tft panel timing vt = vertical total = [(reg[30h] bits 9-0) + 1] lines vps = fpframe pulse start position = (reg[3ch] bits 9-0) lines vpw = fpframe pulse width = [(reg[3ch] bits 18-16) + 1] lines vdps = vertical display period start position= (reg[38h] bits 9-0) lines vdp = vertical display period = [(reg[34h] bits 9-0) + 1] lines ht = horizontal total = [((reg[20h] bits 6-0) + 1) x 8] pixels hps = fpline pulse start position = [(reg[2ch] bits 9-0) + 1] pixels hpw = fpline pulse width = [(reg[2ch] bits 22-16) + 1] pixels hdps = horizontal display period start position= [(reg[28h] bits 9-0) + 5] pixels hdp = horizontal display period = [((reg[24h] bits 6-0) + 1) x 8] pixels *for tft panels, the hdp must be a minimum of 8 pixels and must be increased by multiples of 8. *panel type bits (reg[0ch] bits 1-0) = 01 (tft) *fpline pulse polarity bit (reg[2ch] bit 23) = 0 (active low) *fpframe polarity bit (reg[3ch] bit 23) = 0 (active low) fpframe vt (= 1 frame) drdy fpline drdy fpline vdps vps vpw vdp ht (= 1 line) hps hdps hdp fpdat[17:0] fpdat[17:0] invalid invalid fpshift hpw epson research and development page 67 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 6.5.9 9/12/18-bit tft panel timing figure 6-29: 18-bit tft panel timing vdp = vertical display period = vdp lines vndp = vertical non-display period = vndp1 + vndp2 = vt - vdp lines vndp1 = vertical non-display period 1 = vndp - vndp2 lines vndp2 = vertical non-display period 2 = vdps - vps lines if negative add vt hdp = horizontal display period = hdp ts hndp = horizontal non-display period = hndp1 + hndp2 = ht - hdp ts hndp1 = horizontal non-display period 1 = hdps - hps ts if negative add ht hndp2 = horizontal non-display period 2 = hps - (hdp + hdps) ts if negative add ht fpframe fpline line1 line480 1-1 1-2 1-320 fpline fpshift drdy fpdat[17:0] vdp drdy note: drdy is used to indicate the first pixel example timing for 18-bit 320x240 panel vndp 2 hdp hndp 1 hndp 2 line240 vndp 1 fpdat[17:0] invalid invalid page 68 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 figure 6-30: tft a.c. timing t3 t5 fpline t1 t4 fpframe drdy fpshift 320 t2 fpline 2 1319 t13 t10 t11 t14 t15 t16 t7 t8 t9 t12 fpdat[17:0] note: drdy is used to indicate the first pixel t6 invalid invalid epson research and development page 69 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. ts = pixel clock period 2. t6min = hdps - hps if negative add ht 3. t8min = hps - (hdp + hdps) if negative add ht table 6-27: tft a.c. timing symbol parameter min typ max units t1 fpframe cycle time vt lines t2 fpframe pulse width low vpw lines t3 fpframe falling edge to fpline falling edge phase difference hps ts (note 1) t4 fpline cycle time ht ts t5 fpline pulse width low hpw ts t6 fpline falling edge to drdy active note 2 250 ts t7 drdy pulse width hdp ts t8 drdy falling edge to fpline falling edge note 3 ts t9 fpshift period 1 ts t10 fpshift pulse width high 0.5 ts t11 fpshift pulse width low 0.5 ts t12 fpline setup to fpshift falling edge 0.5 ts t13 drdy to fpshift falling edge setup time 0.5 ts t14 drdy hold from fpshift falling edge 0.5 ts t15 data setup to fpshift falling edge 0.5 ts t16 data hold from fpshift falling edge 0.5 ts page 70 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.10 sharp hr-tft panel timing figure 6-31: sharp hr-tft panel horizontal timing 1. ts = pixel clock period 2. t1typ = [(reg[20h] bits 6-0) + 1] * 8 3. t2typ = [((reg[24h] bits 6-0) + 1) * 8] + 1 4. t3typ = [(reg[24h] bits 6-0) + 1] * 8 table 6-28: sharp hr-tft panel horizontal timing symbol parameter min typ max units t1 horizontal total period 8 note 2 1024 ts (note 1) t2 fpshift (dclk) active 9 note 3 1025 ts t3 horizontal display period 8 note 4 1024 ts t4 gpio3 (spl) pulse width 1 ts t5 fpline (lp) pulse width 1 note 5 256 ts t6 fpline (lp) falling edge to gpio3 (spl) rising edge 2 note 6 - ts t7 gpio1 (cls) pulse width 0 note 7 511 ts t8 gpio1 (cls) falling edge to gpio0 (ps1) rising edge 0 note 8 63 ts t9 gpio0 (ps2) toggle width 0 note 9 127 ts t10 gpio0 (ps2) first falling edge to gpio0 (ps2) first rising edge 0 note 10 255 ts t11 gpio0 (ps3) pulse width 0 note 11 127 ts t12 gpio2 (rev) toggle position to fpline (lp) rising edge 0 note 12 31 ts 123 last fpshift fpdat[17:0] gpio3 fpline gpio1 ps1 ps2 ps3 gpio2 ts t1 (dclk) (ob[5:0], og[5:0], or[5:0]) (spl) (lp) (cls) (rev) gpio0 (ps) t2 t3 t4 t5 t6 t7 t8 t10 t11 t12 t12 t9 t9 t9 t9 t9 epson research and development page 71 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 5. t5typ = (reg[2ch] bits 22-16) + 1 6. t6typ = (reg[28h] bits 9-0) - (reg[2ch] bits 22-16) + 2 7. t7typ = (reg[a0h] bits 8-0) 8. t8typ = (reg[a4h] bits 5-0) 9. t9typ = (reg[ach] bits 6-0) 10. t10typ = (reg[a8h] bits 7-0) 11. t11typ = (reg[b0h] bits 6-0) 12. t12typ = (reg[b4h] bits 4-0) figure 6-32: sharp hr-tft panel vertical timing 1. lines = 1 horizontal line 2. ts = pixel clock period 3. t1typ = (reg[3ch] bits 18-16) + 1 4. t2typ = (reg[30h] bits 9-0) + 1 5. t3typ the fpframe (sps) rising/falling edge can occur before or after fpline (lp) rising edge depending on the value stored in the fpline pulse start position bits (reg[2ch] bits 9-0). to obtain the case indicated by t3, set the fpline pulse start position bits to 0 and the fpframe (sps) rising/falling edge will occur 1 ts before the fpline (lp) rising edge. to obtain the case indicated by t4, set the fpline pulse start position bits to a value between 1 and the horizontal total - 1. then t4 = (horizontal total period - 1) - (reg[2ch] bits 9-0) 6. t5typ = (reg[38h] bits 9-0) 7. t6typ = (reg[34h] bits 9-0) + 1 8. t7typ = (reg[b8h] bits 2-0) table 6-29: sharp hr-tft panel vertical timing symbol parameter min typ max units t1 fpframe (sps) pulse width 1 note 3 8 lines (note 1) t2 vertical total period 1 note 4 1024 lines t3 fpframe (sps) rising/falling edge to fpline (lp) rising edge 1 (note 5) ts (note 2) t4 fpline (lp) rising edge to fpframe (sps) rising/falling edge 0 note 5 1023 ts t5 vertical display start position 0 note 6 1023 lines t6 vertical display period 1 note 7 1024 lines t7 extra driving period for gpio0 (ps1/2) 0 note 8 7 lines driving period for ps3 driving period for ps3 t7 driving period for ps1 or ps2 vertical display period t6 t5 t1 t2 line 1 last fpframe fpline (sps) (lp) fpdat[17:0] (ob[5:0], og[5:0], or[5:0]) t4 t4 t3 t3 t3 page 72 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.11 casio tft panel timing figure 6-33: casio tft horizontal timing 1. ts = pixel clock period 2. t1typ = [(reg[2ch] bits 9-0) + 1) 3. t2typ = [(reg[20h] bits 6-0) + 1) * 8 4. t3typ = [(reg[2ch] bits 22-16) + 1 5. t4typ = depends on the pixel clock (pclk) table 6-30: casio tft horizontal timing symbol parameter min typ max units t1 horizontal pulse start position 1 note 2 1024 ts (note 1) t2 horizontal total 8 note 3 1024 ts t3 horizontal pulse width 1 note 4 128 ts t4 pixel clock period note 5 ts t5 horizontal display period start position 4 note 6 1027 ts t6 horizontal display period 8 note 7 1024 ts t7 fpline (gpck) rising edge to gpio3 (sth) rising edge 0 note 8 63 ts t8 gpio3 (sth) pulse width 1 ts t9 fpline (gpck) rising edge to gpio1 (gres) falling edge 0 note 9 63 ts t10 gpio1 (gres) falling edge to fpline (gpck) rising edge 1 note 10 64 ts t11 fpline (gpck) rising edge to gpio2 (frp) toggle point 0 note 11 127 ts t2 t1 vertical timing fpframe fpline horizontal timing fpline fpshift fpdat[17:0] gpio3 gpio0 gpio1 gpio2 (gsrt) (gpck) (gpck) (clk) (sth) (pol) (gres) (frp) t3 t4 t5 t6 t7 t8 t11 t10 t9 epson research and development page 73 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 6. t5typ = (reg[28h] bits 9-0) + 4 7. t6typ = [(reg[24h] bits 6-0) + 1] * 8 8. t7typ = (reg[c0h] bits 29-24) 9. t9typ = (reg[c0h] bits 5-0) 10. t10typ = (reg[c0h] bits 13-8) + 1 11. t11typ = (reg[c0h] bits 22-16) figure 6-34: casio tft vertical timing 1. lines = 1 horizontal line 2. t1typ = (reg[30h] bits 9-0) + 1 3. t2typ = (reg[3ch] bits 9-0) 4. t3typ = (reg[3ch] bits 18-16) + 1 5. t4typ = (reg[38h] bits 9-0) + 1 6. t5typ = (reg[34h] bits 9-0) + 1 table 6-31: casio tft vertical timing symbol parameter min typ max units t1 vertical total 1 note 2 1024 lines (note 1) t2 vertical pulse start 0 note 3 1023 lines t3 vertical pulse width 1 note 4 8 lines t4 vertical display period start position 1 note 5 1024 lines t5 vertical display period 1 note 6 1024 lines t5 t4 t1 t2 t3 fpframe fpline gpio1 gpio2 gpio0 fpdat[17:0] (gsrt) (gpck) (gres) (frp) (pol) page 74 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.12 tft type 2 panel timing figure 6-35: tft type 2 horizontal timing table 6-32: tft type 2 horizontal timing symbol parameter min typ max units t1 horizontal total period 1 note 2 1024 ts (note 1) t2 fpline (stb) pulse width 5 ts t3 gpio0 (vclk) rising edge to fpline (stb) rising edge 7 note 3 16 ts t4 fpline (stb) rising edge to gpio0 (vclk) falling edge 7 note 4 16 ts t5 fpline (stb) rising edge to gpio3 (sth) rising edge note 5 ts t6 gpio3 (sth) pulse width 1 ts t7 data setup time 0.5 ts t8 data hold time 0.5 ts t9 horizontal display period 8 note 6 1024 ts t10 fpline (stb) rising edge to gpio1 (ap) rising edge 40 note 7 90 ts t11 gpio1 (ap) pulse width 20 note 8 270 ts t12 fpline (stb) rising edge to gpio2 (pol) toggle position 10 ts fpline gpio0 gpio3 gpio2 d[17:0] gpio1 t1 t2 t3 t4 t5 t6 t7 t10 t11 t12 drdy 2 1 t8 t9 last fpshift (stb) (vclk) (sth) (clk) (pol) (ap) (inv) epson research and development page 75 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. ts = pixel clock period 2. t1typ = [(reg[20h] bits 6-0) + 1] * 8 3. t3typ = (reg[bch] bits 1-0) selected from 7, 9, 12 or 16 ts 4. t4typ = (reg[bch] bits 4-3) selected from 7, 9, 12 or 16 ts 5. t5typ = (reg[28h] bits 9-0) + 3 ts 6. t9typ = [(reg[24h] bits 6-0) + 1] * 8 7. t10typ = (reg[bch] bits 9-8) selected from 40, 52, 68 or 90 ts 8. t11typ = (reg[bch] bits 13-11) selected from 20, 40, 80, 120, 150, 190, 240 or 270 ts figure 6-36: tft type 2 vertical timing 1. ts = pixel clock period 2. lines = 1 horizontal line 3. t4typ = (reg[38h] bits 9-0) 4. t5typ = (reg[34h] bits 9-0) table 6-33: tft type 2 vertical timing symbol parameter min typ max units t1 vertical total period 8 1024 lines t2 fpframe (stv) pulse width 1 lines t3 gpio3 (sth) rising edge to fpframe (stv) rising edge 0 ts (note 1) t4 vertical display start position 0 note 3 1024 lines (note 2) t5 vertical display period 1 note 4 1024 ts fpframe gpio3 (pol) gpio2 d[17:0] (alternate timing) line2 line1 t1 t2 t3 t4 t5 (even frame) last gpio2 gpio2 (stv) (sth) (odd frame) (pol) (pol) page 76 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.13 tft type 3 panel timing figure 6-37: tft type 3 horizontal timing fpline gpio3 gpio1 gpio2 d[17:0] gpo1 2 1 t1 t2 t3 t5 t4 t6 t7 t8 t11 t12 drdy fpshift gpio0 t14 t9 t10 t13 (lp) (eio) (cph) (inv) (oe) (pol) (vcom) (cpv) epson research and development page 77 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. ts = pixel clock period 2. t1typ = [(reg[20h] bits 6-0) + 1] * 8 3. t2typ = (reg[2ch] bits 22-16) + 1 3. t3typ = (reg[28h] bits 9-0) + 4 ts 4. t4typ = selected from 0, 1, 2 ts 6. t8typ = [(reg[24h] bits 6-0) + 1] * 8 7. t9typ = (reg[d8h] bits 15-8) * 2 8. t10typ = (reg[d8h] bits 23-16) * 2 9. t11typ = (reg[d8h] bits 31-24) * 2 10. t12typ = (reg[dch] bits 7-0) * 2 7. t14typ = (reg[dch] bits 15-8) * 2 table 6-34: tft type 3 horizontal timing symbol parameter min typ max units t1 horizontal total period 8 1024 ts (note 1) t2 fpline (lp) pulse width 1 256 ts t3 fpline (lp) rising edge to gpio3 (eio) rising edge ts t4 gpio3 (eio) pulse width 1 ts t5 gpio3 (eio) rising edge to 1st data 1 ts t6 data setup time 0.5 ts t7 data hold time 0.5 ts t8 horizontal display period 8 1024 ts t9 fpline (lp) rising edge to gpio1 (oe) rising edge 0 512 ts t10 gpio1 (oe) pulse width 0 512 ts t11 fpline (lp) rising edge to gpio2 (pol) toggle position 0 512 ts t12 fpline (lp) rising edge to gpo1 (vcom) toggle position 0 512 ts t13 fpline (lp) rising edge to gpio0 (cpv) rising edge 0 ts t14 gpio0 (cpv) pulse width 0 512 ts page 78 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 figure 6-38: tft type 3 vertical timing fpframe gpio0 gpio1 d[17:0] line2 line1 t1 t2 t3 t4 t6 last gpo2 gpio2 t3 t7 gpo1 fpline t5 (odd frame) (even frame) gpio2 gpo1 (odd frame) (even frame) t5 (stv) (cpv) (lp) (oe) (xoev) (pol) (pol) (vcom) (vcom) epson research and development page 79 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 1. ts = pixel clock period 2. t4typ = (reg[38h] bits 9-0) 2. t5typ = (reg[34h] bits 9-0) + 1 3. t6typ = (reg[dch] bits 23-16) * 2 4. t7typ = (reg[dch] bits 31-24) * 2 table 6-35: tft type 3 vertical timing symbol parameter min typ max units t1 vertical total period 1 1024 lines t2 fpframe (stv) pulse width 1 lines t3 gpio0 (cpv) rising edge to fpframe (stv) rising (falling) edge 0.5 lines t4 vertical display start position 1 lines t5 vertical display period 1 1024 lines t6 gpo2 (xoev) rising edge to gpio0 (cpv) rising edge 0 512 ts t7 gpio0 (cpv) rising edge to gpo2 (xoev) falling edge 0 512 ts page 80 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 6.5.14 tft type 4 panel timing figure 6-39: tft type 4 panel timing vdp = vertical display period = vdp lines vndp = vertical non-display period = vndp1 + vndp2 = vt - vdp lines vndp1 = vertical non-display period 1 = vndp - vndp2 lines vndp2 = vertical non-display period 2 = vdps - vps lines if negative add vt hdp = horizontal display period = hdp ts hndp = horizontal non-display period = hndp1 + hndp2 = ht - hdp ts hndp1 = horizontal non-display period 1 = hdps - (hps + 1) + 5 ts if negative add ht hndp2 = horizontal non-display period 2 = (hps + 1) - (hdp + hdps + 5) ts if negative add ht fpframe fpline line1 line480 1-1 1-2 1-640 fpline fpshift drdy fpdat[17:0] vdp drdy note: drdy is used to indicate the first pixel example timing for 12-bit 640x480 panel vndp 2 hdp hndp 1 hndp 2 line480 vndp 1 fpdat[17:0] invalid invalid epson research and development page 81 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 6-40: tft type 4 a.c. timing t3 t5 fpline t1 t4 fpframe drdy fpshift 640 t2 fpline 2 1639 t14 t11 t12 t15 t16 t17 t8 t9 t10 t13 fpdat[17:0] note: drdy is used to indicate the first pixel t6 invalid invalid t7 page 82 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 1. ts = pixel clock period 2. t6min = hdps - (hps + 1) + 5 if negative add ht 3. t8min = (hps + 1) - (hdp + hdps + 5) if negative add ht table 6-36: tft type 4 a.c. timing symbol parameter min typ max units t1 fpframe cycle time vt lines t2 fpframe pulse width low vpw lines t3 fpframe falling edge to fpline falling edge phase difference hps + 1 ts (note 1) t4 fpline cycle time ht ts t5 fpline pulse width low hpw ts t6 fpline falling edge to drdy active note 2 250 ts t7 drdy active to data setup 8 ts t8 drdy pulse width hdp ts t9 drdy falling edge to fpline falling edge note 3 ts t10 fpshift period 1 ts t11 fpshift pulse width high 0.5 ts t12 fpshift pulse width low 0.5 ts t13 fpline setup to fpshift falling edge 0.5 ts t14 drdy to fpshift falling edge setup time 0.5 ts t15 drdy hold from fpshift falling edge 0.5 ts t16 data setup to fpshift falling edge 0.5 ts t17 data hold from fpshift falling edge 0.5 ts epson research and development page 83 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 6.6 usb timing figure 6-41 data signal rise and fall time figure 6-42 differential data jitter figure 6-43 differential to eop transition skew and eop width data signal rise and fall time page 84 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 figure 6-44 receiver jitter tolerance 1 measured from 10% to 90% of the data signal. 2 the rising and falling edges should be smoothly transitioning (monotonic). 3 timing difference between the differential data signals. 4 measured at crossover point of differential data signals. 520 is placed in series to meet this usb specification. the actual driver output impedance is 15 . table 6-37 usb interface timing symbol parameter conditions waveform min typ max unit usb freq usb clock frequency 48 mhz t period usb clock period figure 6-41 t r rise & fall times c l = 50 pf notes 1,2 figure 6-41 420ns t f 420 t rfm rise/fall time matching (t r / t f ) figure 6-41 90 110 % v crs output signal crossover voltage 1.3 2.0 v z drv driver output resistance steady state drive 28 note 5 44 t drate data rate 11.97 12 12.03 mbs t ddj1 source differential driver jitter to next transition notes 3,4. figure 6-42 -3.5 0 3.5 ns t ddj2 source differential driver jitter for paired transitions notes 3,4 figure 6-42 -4.0 0 4.0 ns t deop differential to eop transition skew note 4 figure 6-43 -2 0 5 ns t eopt source eop width note 4 figure 6-43 160 167 175 ns t jr1 receiver data jitter tolerance to next transition note 4 figure 6-44 -18.5 0 18.5 ns t jr2 receiver data jitter tolerance for paired transitions note 4 figure 6-44 -9 0 9 ns t eopr1 eop width at receiver; must reject as eop note 4 figure 6-43 40 ns t eopr2 eop width at receiver; must accept as eop note 4 figure 6-43 80 ns 1 usb freq ------------------------- epson research and development page 85 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 7 clocks 7.1 clock descriptions 7.1.1 bclk bclk is an internal clock derived from clki or clki2 (see reg[04h] bit 0). if clki is selected as the source, bclk can be a divided version ( 1, 2) of clki. clki is typically derived from the host cpu bus clock. the source clock options for bclk may be selected as in the following table. note for synchronous bus interfaces, it is recommended that bclk be set the same as the cpu bus clock (not a divided version of clki) e.g. sh-3, sh-4. 7.1.2 mclk mclk provides the internal clock required to access the embedded sram. the s1d13a05 is designed with efficient power saving control for clocks (clocks are turned off when not used); reducing the frequency of mclk does not necessarily save more power. furthermore, reducing the mclk frequency relative to the bclk frequency increases the cpu cycle latency and so reduces screen update performance. for a balance of power saving and performance, the mclk should be configured to have a high enough frequency setting to provide sufficient screen refresh as well as acceptable cpu cycle latency. note the maximum frequency of mclk is 50mhz (30mhz if running core v dd at 2.0v 10%). as mclk is derived from bclk, when bclk is greater than 50mhz, mclk must be divided using reg[04h] bits 5-4. the source clock options for mclk may be selected as in the following table. table 7-1: bclk clock selection source clock options bclk selection clki cnf6 = 0 clki 2 cnf6 = 1 table 7-2: mclk clock selection source clock options mclk selection bclk reg[04h] bits 5-4 = 00 bclk 2 reg[04h] bits 5-4 = 01 bclk 3 reg[04h] bits 5-4 = 10 bclk 4 reg[04h] bits 5-4 = 11 page 86 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 7.1.3 pclk pclk is the internal clock used to control the panel. it should be chosen to match the optimum frame rate of the panel. see section 10, ?frame rate calculation? on page 162 for details on the relationship between pclk and frame rate. some flexibility is possible in the selection of pclk. firstly, panels typically have a range of permissible frame rates. secondly, it may be possible to choose a higher pclk frequency and tailor the horizontal non-display period to bring down the frame-rate to its optimal value. the source clock options for pclk may be selected as in the following table. table 7-3: pclk clock selection source clock options pclk selection mclk reg[08h] bits 7-0 = 00h mclk 2 reg[08h] bits 7-0 = 10h mclk 3 reg[08h] bits 7-0 = 20h mclk 4 reg[08h] bits 7-0 = 30h mclk 8 reg[08h] bits 7-0 = 40h bclk reg[08h] bits 7-0 = 01h bclk 2 reg[08h] bits 7-0 = 11h bclk 3 reg[08h] bits 7-0 = 21h bclk 4 reg[08h] bits 7-0 = 31h bclk 8 reg[08h] bits 7-0 = 41h clki reg[08h] bits 7-0 = 02h clki 2 reg[08h] bits 7-0 = 12h clki 3 reg[08h] bits 7-0 = 22h clki 4 reg[08h] bits 7-0 = 32h clki 8 reg[08h] bits 7-0 = 42h clki2 reg[08h] bits 7-0 = 03h clki2 2 reg[08h] bits 7-0 = 13h clki2 3 reg[08h] bits 7-0 = 23h clki2 4 rreg[08h] bits 7-0 = 33h clki2 8 reg[08h] bits 7-0 = 43h epson research and development page 87 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 there is a relationship between the frequency of mclk and pclk that must be maintained. 7.1.4 pwmclk pwmclk is the internal clock used by the pulse width modulator for output to the panel. the source clock options for pwmclk may be selected as in the following table. for further information on controlling pwmclk, see ?pwm clock configuration register? on page 121.. table 7-4: relationship between mclk and pclk swivelview orientation color depth (bpp) mclk to pclk relationship swivelview 0 and 180 16 f mclk f pclk 8f mclk f pclk 2 4f mclk f pclk 4 2f mclk f pclk 8 1f mclk f pclk 16 swivelview 90 and 270 16/8/4/2/1 f mclk 1.25 f pclk table 7-5: pwmclk clock selection source clock options pwmclk selection clki reg[70h] bits 2-1 = 00 clki2 reg[70h] bits 2-1 = 01 mclk reg[70h] bits 2-1 = 10 pclk reg[70h] bits 2-1 = 11 page 88 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 7.2 clock selection the following diagram provides a logical representation of the s1d13a05 internal clocks used for the lcd controller. figure 7-1: clock selection note 1 cnf6 must be set at reset#. clki clki2 2 0 1 bclk 2 3 4 00 01 10 11 mclk 00 01 10 11 2 3 4 000 001 010 011 8 1xx pclk pwmclk reg[08h] bits 1,0 reg[70h] bits 2-1 reg[08h] bits 6-4 reg[04h] bits 5-4 cnf6 1 00 01 10 11 0 1 reg[04h] bit 0 epson research and development page 89 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 7.3 clocks versus functions table 7-6: ?s1d13a05 internal clock requirements?, lists the internal clocks required for the following s1d13a05 functions. note 1 pwmclk is an optional clock (see section 7.1.4, ?pwmclk? on page 87). table 7-6: s1d13a05 internal clock requirements function bus clock (bclk) memory clock (mclk) pixel clock (pclk) pwm clock (pwmclk) usb clock (usbclk) register read/write required not required not required not required 1 not required memory read/write required required not required not required 1 not required look-up table register read/write required required not required not required 1 not required software power save required not required not required not required 1 not required lcd output required required required not required 1 not required usb register read/write required not required not required not required required page 90 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 8 registers this section discusses how and where to access the s1d13a05 registers. it also provides detailed information about the layout and usage of each register. 8.1 register mapping the s1d13a05 registers are memory-mapped. when the system decodes the input pins as cs# = 0 and m/r# = 0, the registers may be accessed. the register space is decoded by ab[17:0] and is mapped as follows. table 8-1: s1d13a05 register mapping m/r# address size function 1 00000h to 40000h 256k bytes sram memory 0 0000h to 00e3h 227 bytes configuration registers 0 4000h to 4054h 84 bytes usb registers 0 8000h to 8019h 25 bytes 2d acceleration registers 0 10000h to 1fffeh 65536 bytes (64k bytes) 2d accelerator data port epson research and development page 91 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.2 register set the s1d13a05 register set is as follows. table 8-2: s1d13a05 register set register pg register pg lcd register descriptions (offset = 0h) read-only configuration registers reg[00h] product information register 93 clock configuration registers reg[04h] memory clock configuration register 94 reg[08h] pixel clock configuration register 95 panel configuration registers reg[0ch] panel type & mod rate register 96 reg[10h] display settings register 97 reg[14h] power save configuration register 100 look-up table registers reg[18h] look-up table write register 101 reg[1ch] look-up table read register 102 display mode registers reg[20h] horizontal total register 103 reg[24h] horizontal display period register 103 reg[28h] horizontal display period start position register 104 reg[2ch] fpline register 104 reg[30h] vertical total register 105 reg[34h] vertical display period register 106 reg[38h] vertical display period start position register 106 reg[3ch] fpframe register 107 reg[40h] main window display start address register 108 reg[44h] main window line address offset register 108 reg[48h] extended panel type register 108 picture-in-picture plus (pip + ) registers reg[50h] pip + window display start address register 110 reg[54h] pip + window line address offset register 110 reg[58h] pip + window x positions register 111 reg[5ch] pip + window y positions register 113 miscellaneous registers reg[60h] reserved 115 reg[64h] gpio status and control register 115 reg[68h] gpo status and control register 119 reg[70h] pwm clock configuration register 121 reg[74h] pwmout duty cycle register 122 reg[80h] scratch pad a register 123 reg[84h] scratch pad b register 123 reg[88h] scratch pad c register 123 extended panel registers reg[a0h] hr-tft cls width register 124 reg[a4h] hr-tft ps1 rising edge register 124 reg[a8h] hr-tft ps2 rising edge register 124 reg[ach] hr-tft ps2 toggle width register 125 reg[b0h] hr-tft ps3 signal width register 125 reg[b4h] hr-tft rev toggle point register 125 reg[b8h] hr-tft ps1/2 end register 126 reg[bch] type 2 tft configuration register 126 reg[c0h] casio tft timing register 129 reg[d8h] type 3 tft configuration 0 register 128 reg[dch] type 3 tft configuration 1 register 129 reg[e0h] type 3 tft pclk divide register 130 reg[e4h] type 3 tft partial mode display control register 131 reg[e8h] type 3 tft partial area 0 positions register 132 reg[ech] type 3 tft partial area 1 positions register 132 reg[f0h] type 3 tft partial area 2 positions register 133 reg[f4h] type 3 tft command store register 133 reg[f8h] type 3 tft miscellaneous register 134 page 92 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 usb register descriptions (offset = 4000h) reg[4000h] control register 135 reg[4002h] interrupt enable register 0 136 reg[4004h] interrupt status register 0 137 reg[4006h] interrupt enable register 1 138 reg[4008h] interrupt status register 1 138 reg[4010h] endpoint 1 index register 139 reg[4012h] endpoint 1 receive mailbox data register 139 reg[4018h] endpoint 2 index register 139 reg[401ah] endpoint 2 transmit mailbox data register 140 reg[401ch] endpoint 2 interrupt polling interval register 140 reg[4020h] endpoint 3 receive fifo data register 140 reg[4022h] endpoint 3 receive fifo count register 140 reg[4024h] endpoint 3 receive fifo status register 141 reg[4026h] endpoint 3 maximum packet size register 141 reg[4028h] endpoint 4 transmit fifo data register 141 reg[402ah] endpoint 4 transmit fifo count register 142 reg[402ch] endpoint 4 transmit fifo status register 142 reg[402eh] endpoint 4 maximum packet size register 142 reg[4030h] endpoint 4 maximum packet size register 142 reg[4032h] usb status register 143 reg[4034h] frame counter msb register 144 reg[4036h] frame counter lsb register 144 reg[4038h] extended register index 144 reg[403ah] extended register data 144 reg[403ah], index[00h] vendor id msb 145 reg[403ah], index[01h] vendor id lsb 145 reg[403ah], index[02h] product id msb 145 reg[403ah], index[03h] product id lsb 145 reg[403ah], index[04h] release number msb 145 reg[403ah], index[05h] release number lsb 145 reg[403ah], index[06h] receive fifo almost full threshold 146 reg[403ah], index[07h] transmit fifo almost empty threshold 146 reg[403ah], index[08h] usb control 146 reg[403ah], index[09h] maximum power consumption 146 reg[403ah], index[0ah] packet control 147 reg[403ah], index[0bh] reserved 148 reg[403ah], index[0ch] fifo control 148 reg[4040h] usbfc input control register 148 reg[4042h] reserved 149 reg[4044h] pin input status / pin output data register 149 reg[4046h] interrupt control enable register 0 149 reg[4048h] interrupt control enable register 1 150 reg[404ah] interrupt control status/clear register 0 150 re g[404ch] interrupt control status/clear register 1 151 reg[404eh] interrupt control masked status register 0 152 reg[4050h] interrupt control masked status register 1 152 reg[4052h] usb software reset register 152 reg[4054h] usb wait state register 152 2d acceleration (bitblt) register descriptions (offset = 8000h) reg[8000h] bitblt control register 153 reg[8004h] bitblt status register 154 reg[8008h] bitblt command register 155 reg[800ch] bitblt source start address register 157 reg[8010h] bitblt destination start address register 157 reg[8014h] bitblt memory address offset register 158 reg[8018h] bitblt width register 158 reg[801ch] bitblt height register 158 reg[8020h] bitblt background color register 159 reg[8024h] bitblt foreground color register 159 2d acceleration (bitblt) data register descriptions (offset = 10000h) ab16-ab0 = 10000h-1fffeh, 2d accelerator (bitblt) data memory mapped region register 160 table 8-2: s1d13a05 register set register pg register pg epson research and development page 93 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.3 lcd register descriptions (offset = 0h) unless specified otherwise, all register bits are set to 0 during power-on. 8.3.1 read-only configuration registers bits 31-26 product code these read-only bits indicate the product code. the product code is 001011 (0bh). bits 25-24 revision code these are read-only bits that indicates the revision code. the revision code is 01. bits 22-16 cnf[6:0] status these read-only status bits return the status of the configuration pins cnf[6:0]. cnf[6:0] are latched at the rising edge of reset#. note for a functional description of each configuration bit (cnf[6:0]), see section 4.3, ?summary of configuration options? on page 25. bits 15-8 display buffer size bits [7:0] this is a read-only register that indicates the size of the sram display buffer measured in 4k byte increments. the s1d13a05 display buffer is 256k bytes and therefore this regis- ter returns a value of 64 (40h). value of this register = display buffer size 4k bytes = 256k bytes 4k bytes = 64 (40h) bits 7-2 product code these read-only bits indicate the product code. the product code is 001011 (0bh). bits 1-0 revision code these are read-only bits that indicates the revision code. the revision code is 01. product information register reg[00h] default = 2dxx402dh read only product code bits 5-0 revision code bits 1-0 n/a cnf[6:0] status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 display buffer size bits 7-0 product code bits 5-0 revision code bits 1-0 1514131211109876543210 page 94 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 8.3.2 clock configuration registers bits 5-4 mclk divide select bits [1:0] these bits determine the divide used to generate the memory clock (mclk) from the bus clock (bclk). bit 0 bclk source select when this bit = 0, the source of the bus clock (bclk) is input pin clki or a divided down version of clki. clki may be divided down using the clki to bclk divide select configuration pin cnf6. when this bit = 1, the source of the bus clock (bclk) is input pin clki2. note changing this bit allows the bclk source to be switched in a glitch-free manner. memory clock configuration register reg[04h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a mclk divide select bits 1-0 n/a bclk source select 15 14 13 12 11 10 9 8 7 654 3 2 10 table 8-3: mclk divide selection mclk divide select bits bclk to mclk frequency ratio 00 1:1 01 2:1 10 3:1 11 4:1 epson research and development page 95 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 6-4 pclk divide select bits [1:0] these bits determine the divide used to generate the pixel clock (pclk) from the pixel clock source. bits 1-0 pclk source select bits [1:0] these bits determine the source of the pixel clock (pclk). pixel clock configuration register reg[08h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a pclk divide select bits 2-0 n/a pclk source select bits 1-0 15 14 13 12 11 10 9 8 7654 3 210 table 8-4: pclk divide selection pclk divide select bits pclk so urce to pclk frequency ratio 000 1:1 001 2:1 010 3:1 011 4:1 1xx 8:1 table 8-5: pclk source selection pclk source select bits pclk source 00 mclk 01 bclk 10 clki 11 clki2 page 96 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 8.3.3 panel confi guration registers bit 24 fpshift invert this bit inverts the fpshift signal used by active panels. for passive panels, this bit has no effect. when this bit is 0, fpshift is unchanged. when this bit is 1, fpshift is inverted. bits 21-16 mod rate bits [5:0] these bits are for passive lcd panels only. when these bits are all 0, the mod output signal (drdy) toggles every fpframe. for a non-zero value n , the mod output signal (drdy) toggles every n fpline. bit 8 hr-tft ps mode this bit is for hr-tft panels only. this bit selects the timing used for the ps signal. the alternate ps timings (ps1, ps2, ps3) result in additional power savings on the hr-tft panel. when this bit = 0, the ps signal uses ps1 timing. when this bit = 1, the ps signal uses ps2 timing. bit 7 panel data format select when this bit = 0, 8-bit single color passive lcd panel data format 1 is selected. for ac timing see section 6.5.5, ?single color 8-bit panel timing (format 1)? on page 60. when this bit = 1, 8-bit single color passive lcd panel data format 2 is selected. for ac timing see section 6.5.6, ?single color 8-bit panel timing (format 2)? on page 62. bit 6 color/mono panel select when this bit = 0, a monochrome lcd panel is selected. when this bit = 1, a color lcd panel is selected. bits 5-4 panel data width bits [1:0] these bits select the data width size of the lcd panel. panel type & mod rate register reg[0ch] default = 00000000h read/write n/a fpshift invert n/a mod rate bits 5-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a hr-tft ps mode panel data format select color/ mono panel select panel data width bits 1-0 reserv ed n/a panel type bits 1-0 15 14 13 12 11 10 9876543 210 table 8-6: panel data width selection panel data width bits [1:0] passive panel data width size active panel data width size 00 4-bit 9-bit 01 8-bit 12-bit 10 16-bit 18-bit 11 reserved reserved epson research and development page 97 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 3 reserved. this bit must be set to 0. bits 1-0 panel type bits[1:0] these bits select the panel type. bit 25 pixel doubling vertical enable this bit controls the pixel doubling feature for the vertical dimension or height of the panel (i.e. 160 pixel high data doubled to 320 pixel high panel). when this bit = 1, pixel doubling in the vertical dimension (height) is enabled. when this bit = 0, there is no hardware effect. note pixel doubling is not supported in swivelview 90 or swivelview 270 modes. bit 24 pixel doubling horizontal enable this bit controls the pixel doubling feature for the horizontal dimension or width of the panel (i.e. 160 pixel wide data doubled to 320 pixel wide panel) when this bit = 1, pixel doubling in the horizontal dimension (width) is enabled. when this bit = 0, there is no hardware effect. note pixel doubling is not supported in swivelview 90 or swivelview 270 modes. table 8-7: lcd panel type selection panel type bits [1:0] panel type 00 stn 01 tft 10 reserved 11 hr-tft display settings register reg[10h] default = 00000000h read/write n/a pixel doubling vertical pixel doubling horiz. display blank dithering disable display blank polarity sw video invert pip + window enable n/a swivelview mode select 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a bits-per-pixel select (actual value: 1, 2, 4, 8 or 16 bpp) 15 14 13 12 11 10 9 8 7 6 543210 page 98 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 23 display blank when this bit = 0, the lcd display pipeline is enabled. when this bit = 1, all applicable lcd data outputs (see table 4-9: ?lcd interface pin mapping,? on page 27) are forced to zero or one. the following table summarizes the changes to the signals on fpdat[17:0] for each combination of bits. bit 22 dithering disable when this bit = 0, dithering on the passive lcd panel is enabled, allowing a maximum of 64k colors (2 18 ) or 64 gray shades in 1/2/4/8 bpp mode. in 16bpp mode, only 64k colors (2 16 ) can also be achieved. when this bit = 1, dithering on the passive lcd panel is disabled, allowing a maximum of 4096 colors (2 12 ) or 16 gray shades. the dithering algorithm provides more shades of each primary color. note for a summary of the results of dithering for each color depth, see table 8-10: ?lcd bit-per-pixel selection,? on page 99. bit 21 display blank polarity when this bit = 0, the display blank function operates normally. when this bit = 1, the display blank function switches polarity. this bit works in conjunction with bit 23 and bit 20. table 8-8: ?display control sum- mary? summarizes the changes to the signals on fpdat[17:0] for each combination of bits. bit 20 software video invert when this bit = 0, video data is normal. when this bit = 1, video data is inverted. this bit works in conjunction with bit 23 and bit 21. table 8-8: ?display control sum- mary? summarizes the changes to the signals on fpdat[17:0] for each combination of bits. note video data is inverted after the look-up table table 8-8: display control summary display blank (reg[10h] bit 23) display blank polarity (reg[10h] bit 21) software video invert (reg[10h] bit 20) output data lines (fpdat[17:0]) 0x 0normal 1inverted 1 0 0 all 0 1 all 1 1 0 all 1 1 all 0 epson research and development page 99 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 19 pip+ window enable this bit enables a pip+ window within the main window. the location of the pip+ win- dow within the landscape window is determined by the pip+ x position register (reg[58h]) and pip+ y position register (reg[5ch]). the pip+ window has its own dis- play start address register (reg[50h]) and memory address offset register (reg[54h]). the pip+ window shares the same color depth and swivelview tm orientation as the main window. bit 17-16 swivelview mode select bits [1:0] these bits select different swivelview tm orientations: bits 4-0 bit-per-pixel select bits [4:0] these bits select the color depth (bit-per-pixel) for the displayed data for both the main window and the pip + window (if active). 1, 2, 4 and 8 bpp modes use the 18-bit lut. 16 bpp mode bypasses the lut. for further details on the lut, refer to section 12, ?look-up table architecture? on page 164. table 8-9: swivelview tm mode select options swivelview mode select bits swivelview orientation 00 0 (normal) 01 90 10 180 11 270 table 8-10: lcd bit-per-pixel selection bit-per-pixel select bits [4:0] color depth (bpp) max. no. of simultaneously displayed colors/shades 00000 reserved 00001 1 bpp 2/2 00010 2 bpp 4/4 00011 reserved 00100 4 bpp 16/16 00101 - 00111 reserved 01000 8 bpp 256/64 10000 16 bpp 64k/64 10001 - 11111 reserved page 100 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 7 vertical non-display period status (read-only) this is a read-only status bit. when this bit = 0, the lcd panel output is in a vertical display period. when this bit = 1, the lcd panel output is in a vertical non-display period. bit 6 memory controller power save status (read-only) this read-only status bit indicates the power save state of the memory controller. when this bit = 0, the memory controller is powered up. when this bit = 1, the memory controller is powered down and the mclk source can be turned off. note memory reads/writes are possible during power save mode because the s1d13a05 dy- namically enables the memory controller for display buffer accesses. bit 4 power save mode enable when this bit = 1, the software initiated power save mode is enabled. when this bit = 0, the software initiated power save mode is disabled. at reset, this bit is set to 1. for a summary of power save mode, see section 15, ?power save mode? on page 178. note memory reads/writes are possible during power save mode because the s1d13a05 dy- namically enables the memory controller for display buffer accesses. bit 0 reserved this bit must be set to 0. power save configuration register reg[14h] default = 00000010h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a vndp status (ro) memory power save status (ro) n/a power save enable n/a reserv ed 15 14 13 12 11 10 9 876 54 3 2 10 epson research and development page 101 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.3.4 look-up table registers note the s1d13a05 has three 256-position, 6-bit wide luts, one for each of red, green, and blue (see section 12, ?look-up table architecture? on page 164). note this is a write-only register and returns 00h if read. bits 31-24 lut write address bits [7:0] these bits form a pointer into the look-up table (lut) which is used to write the lut red, green, and blue data. when the s1d13a05 is set to a host bus interface using lit- tle endian (cnf4 = 0), the rgb data is updated to the lut with the completion of a write to these bits. note when a value is written to the lut write address bits, the same value is automatically placed in the lut read address bits (reg[1ch] bits 31-24). bits 23-18 lut red write data bits [5:0] these bits contains the data to be written to the red component of the look-up table. the lut position is controlled by the lut write address bits (bits 31-24). bits 15-10 lut green write data bits [5:0] these bits contains the data to be written to the green component of the look-up table. the lut position is controlled by the lut write address bits (bits 31-24). bits 7-2 lut blue write data bits [5:0] these bits contains the data to be written to the blue component of the look-up table. the lut position is controlled by the lut write address bits (bits 31-24). when the s1d13a05 is set to a host bus interface using big endian (cnf4 = 1), the rgb data is updated to the lut with the completion of a write to these bits. look-up table write register reg[18h] default = 00000000h write only lut write address lut red write data n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lut green write data n/a lut blue write data n/a 15 14 13 12 11 10 9 8765432 1 0 page 102 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 note the s1d13a05 has three 256-position, 6-bit wide luts, one for each of red, green, and blue (see section 12, ?look-up table architecture? on page 164). bits 31-24 lut read address bits [7:0] (write only) this register forms a pointer into the look-up table (lut) which is used to read lut data. red data is read from bits 23-18, green data from bits 15-10, and blue data from bits 7-2. note if a write to the lut write address bits (reg[18h] bits 31-24) is made, the lut read address bits are automatically updated with the same value. bits 23-18 lut red read data bits [5:0] (read only) these bits point to the data from the red component of the look-up table. the lut posi- tion is controlled by the lut read address bits (bits 31-24). this is a read-only register. bits 15-10 lut green read data bits [5:0] (read only) these bits point to the data from the green component of the look-up table. the lut position is controlled by the lut read address bits (bits 31-24). this is a read-only regis- ter. bits 7-2 lut blue read data bits [5:0] (read only) these bits point to the data from the blue component of the look-up table. the lut position is controlled by the lut read address bits (bits 31-24). this is a read-only regis- ter. look-up table read register reg[1ch] default = 00000000h write only (bits 31-24)/read only lut read address (write only) lut red read data n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 lut green read data n/a lut blue read data n/a 15 14 13 12 11 10 9 8765432 1 0 epson research and development page 103 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.3.5 display mode registers bits 6-0 horizontal total bits [6:0] these bits specify the lcd panel horizontal total period, in 8 pixel resolution. the hori- zontal total is the sum of the horizontal display period and the horizontal non-display period. since the maximum horizontal total is 1024 pixels, the maximum panel resolu- tion supported is 800x600. reg[20h] bits 6:0 = (horizontal total in number of pixels 8) - 1 note 1 for all panels this register must be programmed such that: hdps + hdp < ht ht - hdp 8mclk 2 for passive panels, this register must be programmed such that: hps + hpw < ht 3 see section 6.5, ?display interface? on page 52. bits 6-0 horizontal display period bits [6:0] these bits specify the lcd panel horizontal display period, in 8 pixel resolution. the horizontal display period should be less than the horizontal total to allow for a sufficient horizontal non-display period. reg[24h] bits 6:0 = (horizontal display period in number of pixels 8) - 1 note for passive panels, hdp must be a minimum of 32 pixels and must be increased by mul- tiples of 16. for tft panels, hdp must be a minimum of 8 pixels and must be increased by multi- ples of 8. note see section 6.5, ?display interface? on page 52. horizontal total register reg[20h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a horizontal total bits 6-0 15 14 13 12 11 10 9 8 76543210 horizontal display period register reg[24h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a horizontal display period bits 6-0 15 14 13 12 11 10 9 8 76543210 page 104 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 9-0 horizontal display period start position bits [9:0] these bits specify a value used in the calculation of the horizontal display period start position (in 1 pixel resolution) for tft and hr-tft panels. for passive lcd panels these bits must be set to 00h which will result in hdps = 22. hdps = (reg[28h] bits 9-0) + 22 for tft panels, hdps is calculated using the following formula. hdps = (reg[28h] bits 9-0) + 5 note this register must be programmed such that the following formula is valid. hdps + hdp < ht bit 23 fpline pulse polarity this bit selects the polarity of the horizontal sync signal. for passive panels, this bit must be set to 1. for active panels, this bit is set according to the horizontal sync signal of the panel (typically fpline or lp). this bit has no effect for tft type 2 and tft type 3 panels. when this bit = 0, the horizontal sync signal is active low. when this bit = 1, the horizontal sync signal is active high. bits 22-16 fpline pulse width bits [6:0] these bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. the horizontal sync signal is typically fpline or lp, depending on the panel type. reg[2ch] bits 22:16 = fpline pulse width in number of pixels - 1 note for passive panels, these bits must be programmed such that the following formula is valid. hpw + hps < ht note see section 6.5, ?display interface? on page 52. horizontal display period start position register reg[28h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a horizontal display period start position bits 9-0 15 14 13 12 11 109876543210 fpline register reg[2ch] default = 00000000h read/write n/a fpline polarity fpline pulse width bits 6-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a fpline pulse start position bits 9-0 15 14 13 12 11 109876543210 epson research and development page 105 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 9-0 fpline pulse start position bits [9:0] these bits specify the start position of the horizontal sync signal, in 1 pixel resolution. fpline pulse start position in pixels = (reg[2ch] bits 9-0) + 1 note for passive panels, these bits must be programmed such that the following formula is valid. hpw + hps < ht note see section 6.5, ?display interface? on page 52. bits 9-0 vertical total bits [9:0] these bits specify the lcd panel vertical total period, in 1 line resolution. the vertical total is the sum of the vertical display period and the vertical non-display period. the maximum vertical total is 1024 lines. reg[30h] bits 9:0 = vertical total in number of lines - 1 note 1 this register must be programmed such that the following formula is valid. vt > vdps + vdp 2 if an hr-tft panel is selected, the following formula must also apply. vt > (reg[b8h] bits 2-0) + vdp + vps + 1 3 see section 6.5, ?display interface? on page 52. vertical total register reg[30h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a vertical total bits 9-0 15 14 13 12 11 109876543210 page 106 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 9-0 vertical display period bits [9:0] these bits specify the lcd panel vertical display period, in 1 line resolution. the vertical display period should be less than the vertical total to allow for a sufficient vertical non-display period. reg[34h] bits 9:0 = vertical display period in number of lines - 1 note 1 this register must be programmed such that the following formula is valid. vt > vdps + vdp 2 if an hr-tft panel is selected, the following formula must also apply. vt > (reg[b8h] bits 2-0) + vdp + vps + 1 3 see section 6.5, ?display interface? on page 52. bits 9-0 vertical display period start position bits [9:0] these bits specify the vertical display period start position for tft and hr-tft panels in 1 line resolution. for passive lcd panels these bits must be set to 00h. for passive lcd panels these bits must be set to 00h. for tft panels, vdps is calculated using the following formula. vdps = reg[38h] bits 9-0 note 1 this register must be programmed such that the following formula is valid. vt > vdps + vdp 2 if an hr-tft panel is selected, the following formula must also apply. vt > (reg[b8h] bits 2-0) + vdp + vps + 1 3 see section 6.5, ?display interface? on page 52. vertical display period register reg[34h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a vertical display period bits 9-0 15 14 13 12 11 109876543210 vertical display period start position register reg[38h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a vertical display period start position bits 9-0 15 14 13 12 11 109876543210 epson research and development page 107 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 23 fpframe pulse polarity this bit selects the polarity of the vertical sync signal. for passive panels, this bit must be set to 1. for tft panels, this bit is set according to the horizontal sync signal of the panel (typically fpframe, sps). this bit has no effect for tft type 2 panels. when this bit = 0, the vertical sync signal is active low. when this bit = 1, the vertical sync signal is active high. bits 18-16 fpframe pulse width bits [2:0] these bits specify the width of the panel vertical sync signal, in 1 line resolution. the ver- tical sync signal is typically fpframe, or sps, depending on the panel type. reg[3ch] bits 2:0 = fpframe pulse width in number of lines - 1 note see section 6.5, ?display interface? on page 52. bits 9-0 fpframe pulse start position bits [9:0] these bits specify the start position of the vertical sync signal, in 1 line resolution. for passive panels, these bits must be set to 00h. for tft panels, vdps is calculated using the following formula. vps = reg[3ch] bits 9-0 note see section 6.5, ?display interface? on page 52. fpframe register reg[3ch] default = 00000000h read/write n/a fpframe polarity n/a fpframe pulse width bits 2-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a fpframe pulse start position bits 9-0 15 14 13 12 11 1098 7 6543210 page 108 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 16-0 main window display start address bits [16:0] this register specifies the starting address, in dwords, for the lcd image in the display buffer for the main window. note that this is a double-word (32-bit) address. an entry of 00000h into these registers represents the first double-word of display memory, an entry of 00001h represents the sec- ond double-word of the display memory, and so on. calculate the display start address as follows: reg[40h] bits 16:0 = image address 4 (valid only for swivelview 0) note for information on setting this register for other swivelview orientations, see section 13, ?swivelview?? on page 170. bits 9-0 main window line address offset bits [9:0] this register specifies the offset, in dwords, from the beginning of one display line to the beginning of the next display line in the main window. note that this is a 32-bit address increment. calculate the line address offset as follows: reg[44h] bits 9:0 = display width in pixels (32 bpp) note a virtual display can be created by programming this register with a value greater than the formula requires. when a virtual display is created the image width is larger than the display width and the displayed image becomes a window into the larger virtual image. main window display start address register reg[40h] default = 00000000h read/write n/a bit 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 main window display start address bits 15-0 1514131211109876543210 main window line address offset register reg[44h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a main window line address offset bits 9-0 15 14 13 12 11 109876543210 epson research and development page 109 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 8 data compare invert enable this bit can be used to lower power consumption for tft type 2 and tft type 3 inter- faces. the data compare and invert function reduces the amount of data toggled by counting the number of bits that are changed (1 to 0 or 0 to 1) from the previous pixel data. if more than half of the bits are changed the data is inverted and the lesser amount of bits are toggled. for all other panel interfaces it has no effect. when this bit = 0, the data compare and invert functions are disabled. when this bit = 1, the data compare and invert functions are enabled. bits 3-0 extended panel type bits [3:0] these bits override the setting in reg[0ch] bits 1-0 and allow selection of the alternate tft panel types. extended panel type register reg[48h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a data compare invert enable n/a extended panel type bits 3-0 15 14 13 12 11 10 98 7 6 5 43210 table 8-11: extended panel type selection reg[48h] bits [3:0] panel type 0000 no effect from reg[0ch] bits 1-0 0001 tft type 2 0010 tft type 3 0011 tft type 4 0100 casio tft 0101 - 1111 reserved page 110 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 8.3.6 picture-in-picture plus (pip + ) registers bits 16-0 pip + display start address bits [16:0] these bits form the 17-bit address for the starting double-word of the pip+ window. note that this is a double-word (32-bit) address. an entry of 00000h into these registers represents the first double-word of display memory, an entry of 00001h represents the sec- ond double-word of the display memory, and so on. note these bits have no effect unless the pip+ window enable bit is set to 1 (reg[10h] bit 19). bits 9-0 pip + window line address offset bits [9:0] these bits are the lcd display?s 10-bit address offset from the starting double-word of line ?n? to the starting double-word of line ?n + 1? for the pip + window. note that this is a 32-bit address increment. note these bits have no effect unless the pip + window enable bit is set to 1 (reg[10h] bit 19). pip + display start address register reg[50h] default = 00000000h read/write n/a bit 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pip + display start address bits 15-0 1514131211109876543210 pip + line address offset register reg[54h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a pip + line address offset bits 9-0 15 14 13 12 11 109876543210 epson research and development page 111 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 note the effect of reg[58h] through reg[5ch] takes place only after reg[5ch] is written and at the next vertical non-display period. bits 25-16 pip + window x end position bits [9:0] these bits determine the x end position of the pip + window in relation to the origin of the panel. due to the s1d13a05 swivelview feature, the x end position may not be a horizontal position value (only true in 0 and 180 swivelview). for further information on defining the value of the x end position register, see section 14, ?picture-in-picture plus (pip+)? on page 175. the register is also incremented differently based on the swivelview orientation. for 0 and 180 swivelview the x end position is incremented by x pixels where x is relative to the current color depth. for 90 and 270 swivelview the x end position is incremented in 1 line increments. depending on the color depth, some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels. note these bits have no effect unless the pip + window enable bit is set to 1 (reg[10h] bit 19). pip + x positions register reg[58h] default = 00000000h read/write n/a pip + x end position bits 9-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a pip + x start position bits 9-0 15 14 13 12 11 109876543210 table 8-12: 32-bit address increments for color depth color depth pixel increment (x) 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 page 112 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 9-0 pip + window x start position bits [9:0] these bits determine the x start position of the pip + window in relation to the origin of the panel. due to the s1d13a05 swivelview feature, the x start position may not be a horizontal position value (only true in 0 and 180 swivelview). for further information on defining the value of the x start position register, see section 14, ?picture-in-picture plus (pip+)? on page 175. the register is also incremented differently based on the swivelview orientation. for 0 and 180 swivelview the x start position is incremented by x pixels where x is relative to the current color depth. for 90 and 270 swivelview the x start position is incremented in 1 line increments. depending on the color depth, some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels. note these bits have no effect unless the pip + window enable bit is set to 1 (reg[10h] bit 19). table 8-13: 32-bit address increments for color depth color depth pixel increment (x) 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 epson research and development page 113 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 note 1 the effect of reg[58h] through reg[5ch] takes place only after reg[5ch] is written and at the next vertical non-display period. 2 for host bus interfaces using little endian (cnf4 = 0), a write to bits 31-24 causes the pip + window y end position to take effect. for host bus interfaces using big endian (cnf4 = 1), a write to bits 7-0 causes the pip + window y end position to take effect. bits 25-16 pip + window y end position bits [9:0] these bits determine the y end position of the pip + window in relation to the origin of the panel. due to the s1d13a05 swivelview feature, the y end position may not be a vertical position value (only true in 0 and 180 swivelview). for further information on defining the value of the y end position register, see section 14, ?picture-in-picture plus (pip+)? on page 175. the register is also incremented differently based on the swivelview orientation. for 0 and 180 swivelview the y end position is incremented in 1 line increments. for 90 and 270 swivelview the y end position is incremented by y pixels where y is relative to the current color depth. depending on the color depth, some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels. note these bits have no effect unless the pip + window enable bit is set to 1 (reg[10h] bit 19). pip + y positions register reg[5ch] default = 00000000h read/write n/a pip + y end position bits 9-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a pip + y start position bits 9-0 15 14 13 12 11 109876543210 table 8-14: 32-bit address increments for color depth color depth pixel increment (y) 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 page 114 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 9-0 pip + window y start position bits [9:0] these bits determine the y start position of the pip + window in relation to the origin of the panel. due to the s1d13a05 swivelview feature, the y start position may not be a vertical position value (only true in 0 and 180 swivelview). for further information on defining the value of the y start position register, see section 14, ?picture-in-picture plus (pip+)? on page 175. the register is also incremented differently based on the swivelview orientation. for 0 and 180 swivelview the y start position is incremented in 1 line increments. for 90 and 270 swivelview the y start position is incremented by y pixels where y is relative to the current color depth. depending on the color depth, some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels. note these bits have no effect unless the pip + window enable bit is set to 1 (reg[10h] bit 19). table 8-15: 32-bit address increments for color depth color depth pixel increment (y) 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 epson research and development page 115 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.3.7 miscellaneous registers the s1d13a05 gpio pins default to inputs, however they can be individually configured to outputs or inputs using the gpio[7:0] config bits (bits 23-16). if a gpio pin is configured as an input, the input functionality must be enabled using the corresponding gpio[7:0] input enable pin (see bits 31-24). once the gpio pin has been configured, it can be controlled/read using the gpio[7:0] control/status bits (bits 7-0). see the individual bit descriptions for further details. some gpios must be configured as outputs after every reset for use with some extended panel types (i.e. sharp hr-tft, casio tft, etc.). see table 4-9: ?lcd interface pin mapping,? on page 27 and the individual bit descriptions for bits 7-0 for specific infor- mation on each gpio pin. bits 31-24 gpio[7:0] input enable bits these bits individually enable the input function for each gpio pin (gpio[7:0]). after power-on/reset, each bit must be set to a 1 to enable the input function of each gpio pin (default is 0 except for gpio5 which is 1). if the gpio pin is configured as an output the gpio[7:0] input enable bit has no effect. note at power-on/reset, the gpio5 input enable bit (bit 29) defaults to 1. reserved reg[60h] default = 00000000h read/write n/a reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a reserved n/a reserved n/a 15 14 13 12 11 1098765 4 32 1 0 gpio status and control register reg[64h] default = 20000000h read/write gpio7 input enable gpio6 input enable gpio5 input enable gpio4 input enable gpio3 input enable gpio2 input enable gpio1 input enable gpio0 input enable gpio7 config gpio6 config gpio5 config gpio4 config gpio3 config gpio2 config gpio1 config gpio0 config 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a gpio7 control/ status gpio6 control/ status gpio5 control/ status gpio4 control/ status gpio3 control/ status gpio2 control/ status gpio1 control/ status gpio0 control/ status 15 14 13 12 11 10 9 876543210 page 116 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 23-16 gpio[7:0] io configuration at power-on/reset, the gpio[7:0] pins default to inputs. these bits individually configure each gpio pin as either an output or input. when these bits = 0, the associated gpio pin is configured as an input. when these bits = 1, the associated gpio pin is configured as an output. this may be required for some extended panel types (i.e. sharp hr-tft, casio tft, etc.) or usb. see table 4-9: ?lcd interface pin mapping,? on page 27 and the individual bit descriptions for bits 7-0 for specific information on each gpio pin. note if a gpio pin is configured as an input, the input function of the gpio pin must be en- abled using the corresponding gpiox input enable bit (bits 31-24) before the input con- figuration takes effect. bit 7 gpio7 io control/status the following table shows the multiple uses of gpio7. bit 6 gpio6 io control/status the following table shows the multiple uses of gpio6. bit 5 gpio5 io control/status the following table shows the multiple uses of gpio5. table 8-16: gpio7 usage pin usage function output input write 0 write 1 read gpio7 gpio7 driven low gpio7 driven high gpio7 status returned usb not available (used by usbdp) not available (used by usbdp) not available (used by usbdp) table 8-17: gpio6 usage pin usage function output input write 0 write 1 read gpio6 gpio6 driven low gpio6 driven high gpio6 status returned usb not available (used by usbdm) not available (used by usbdm) not available (used by usbdm) table 8-18: gpio5 usage pin usage function output input write 0 write 1 read gpio5 gpio5 driven low gpio5 driven high gpio5 status returned usb not available (used by usbdetect) not available (used by usbdetect) not available (used by usbdetect) epson research and development page 117 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 4 gpio4 io control/status the following table shows the multiple uses of gpio4. bit 3 gpio3 io control/status the following table shows the multiple uses of gpio3. table 8-19: gpio4 usage pin usage function output input write 0 write 1 read gpio4 gpio4 driven low gpio4 driven high gpio4 status returned usb not available (used by usbpup) not available (used by usbpup) not available (used by usbpup) table 8-20: gpio3 usage pin usage function output input write 0 write 1 read gpio3 gpio3 driven low gpio3 driven high gpio3 status returned sharp hr-tft not available (used by spl) not available (used by spl) not available (used by spl) casio tft not available (used by sth) not available (used by sth) not available (used by sth) tft type 2 not available (used by sth) not available (used by sth) not available (used by sth) tft type 3 not available (used by eio) not available (used by eio) not available (used by eio) page 118 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 2 gpio2 io control/status the following table shows the multiple uses of gpio2. bit 1 gpio1 io control/status the following table shows the multiple uses of gpio1. bit 0 gpio0 io control/status the following table shows the multiple uses of gpio0. table 8-21: gpio2 usage pin usage function output input write 0 write 1 read gpio2 gpio2 driven low gpio2 driven high gpio2 status returned sharp hr-tft not available (used by rev) not available (used by rev) not available (used by rev) casio tft not available (used by frp) not available (used by frp) not available (used by frp) tft type 2 not available (used by pol) not available (used by pol) not available (used by pol) tft type 3 not available (used by pol) not available (used by pol) not available (used by pol) table 8-22: gpio1 usage pin usage function output input write 0 write 1 read gpio1 gpio1 driven low gpio1 driven high gpio1 status returned sharp hr-tft not available (used by cls) not available (used by cls) not available (used by cls) casio tft gres forced low gres enabled gres status returned tft type 2 not available (used by ap) not available (used by ap) not available (used by ap) tft type 3 oe forced low oe enabled oe status returned table 8-23: gpio0 usage pin usage function output input write 0 write 1 read gpio0 gpio0 driven low gpio0 driven high gpio0 status returned sharp hr-tft not available (used by ps) not available (used by ps) not available (used by ps) casio tft not available (used by pol) not available (used by pol) not available (used by pol) tft type 2 not available (used by vclk) not available (used by vclk) not available (used by vclk) tft type 3 not available (used by cpv) not available (used by cpv) not available (used by cpv) epson research and development page 119 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 10 gpo10 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo10 high and writing a 0 to this bit drives gpo10 low. a read from this bit returns the status of gpo10. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit sets pdme = 1 and writing a 0 sets pdme = 0. bit 9 gpo9 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo9 high and writing a 0 to this bit drives gpo9 low. a read from this bit returns the status of gpo9. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit sets xstby = 1 and writing a 0 sets xstby = 0. bit 8 gpo8 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo8 high and writing a 0 to this bit drives gpo8 low. a read from this bit returns the status of gpo8. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit sets xohv = 1 and writing a 0 sets xohv = 0. bit 7 gpo7 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo7 high and writing a 0 to this bit drives gpo7 low. a read from this bit returns the status of gpo7. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit sets xresv = 1 and writing a 0 sets xresv = 0. bit 6 gpo6 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo6 high and writing a 0 to this bit drives gpo6 low. a read from this bit returns the status of gpo6. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit sets xresh = 1 and writing a 0 sets xresh = 0. gpo control register reg[68h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a gpo10 control gpo9 control gpo8 control gpo7 control gpo6 control gpo5 control gpo4 control gpo3 control gpo2 control gpo1 control gpo0 control 15 14 13 12 11109876543210 page 120 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 5 gpo5 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo5 high and writing a 0 to this bit drives gpo5 low. a read from this bit returns the status of gpo5. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit enables pclk2 and writing a 0 forces pclk2 low. bit 4 gpo4 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo4 high and writing a 0 to this bit drives gpo4 low. a read from this bit returns the status of gpo4. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit enables pclk1 and writing a 0 forces pclk1 low. bit 3 gpo3 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo3 high and writing a 0 to this bit drives gpo3 low. a read from this bit returns the status of gpo3. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), gpo3 is not available. bit 2 gpo2 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo2 low and writing a 0 to this bit drives gpo2 high . a read from this bit returns the status of gpo2. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit enables xoev and writing a 0 sets xoev = 0 . bit 1 gpo1 control when the type 3 tft lcd interface is not selected (reg[48h] bits 3:0), writing a 1 to this bit drives gpo1 high and writing a 0 to this bit drives gpo1 low. a read from this bit returns the status of gpo1. when the type 3 tft lcd interface is selected (reg[48h] bits 3:0 = 0010), writing a 1 to this bit enables vcom and writing a 0 sets vcom = 0. bit 0 gpo0 control writing a 1 to this bit drives gpo0 high and writing a 0 to this bit drives gpo0 low. a read from this bit returns the status of gpo0. epson research and development page 121 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 figure 8-1: pwm clock block diagram note for further information on pwmclk, see section 7.1.4, ?pwmclk? on page 87. bits 7-4 pwm clock divide select bits [3:0] the value of these bits represents the power of 2 by which the selected pwm clock source is divided. note this divided clock is further divided by 256 before it is output at pwmout. pwm clock configuration register reg[70h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a pwm clock divide select bits 3-0 pwm clock force high pwmclk source select bits 1-0 pwm clock enable 15 14 13 12 11 10 9 8765432 1 0 table 8-24: pwm clock divide select options pwm clock divide select bits [3:0] pwm clock divide amount 0h 1 1h 2 2h 4 3h 8 4h 16 5h 32 6h 64 7h 128 8h 256 9h 512 ah 1024 bh 2048 ch 4096 dh 8192 eh 16384 fh 32768 pwm clock divider pwm duty cycle modulation to pwmout pwmclk divided clock clock source / 2 m m = pwm clock divide select value duty = n / 256 n = pwm clock duty cycle frequency = clock source / (2 m x 256) pwm clock force high pwm clock enable page 122 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 3 pwm clock force high when this bit = 0, the pwmout pin function is controlled by the pwm clock enable bit. when this bit = 1, the pwmout pin is forced to high. bits 2-1 pwmclk source select bits [1:0] these bits determine the source of pwmclk. note for further information on the pwmclk source select, see section 7.2, ?clock selec- tion? on page 88. bit 0 pwm clock enable when this bit = 0, pwmout output acts as a general purpose output pin controllable by bit 3 of reg[70h]. when this bit = 1, the pwm clock circuitry is enabled. note the pwm clock circuitry is disabled when power save mode is enabled. bits 7-0 pwmout duty cycle bits [7:0] this register determines the duty cycle of the pwmout output. table 8-25: pwmclk source selection reg[70h] bits 2-1 pwmclk source 00 clki 01 clki2 10 bclk 11 pclk pwmout duty cycle register reg[74h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a pwmout duty cycle bits 7-0 15 14 13 12 11 10 9 876543210 table 8-26: pwmout duty cycle select options pwmout duty cycle [7:0] pwmout duty cycle 00h always low 01h high for 1 out of 256 clock periods 02h high for 2 out of 256 clock periods ... ... ffh high for 255 out of 256 clock periods epson research and development page 123 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 31-0 scratch pad a bits [31:0] this register contains general purpose read/write bits. these bits have no effect on hard- ware. note the contents of the scratch pad a register defaults to an un-defined state after initial power-up. any data written to this register remains intact when the s1d13a05 is reset, as long as the chip is not powered off . bits 31-0 scratch pad b bits [31:0] this register contains general purpose read/write bits. these bits have no effect on hard- ware. note the contents of the scratch pad b register defaults to an un-defined state after initial power-up. any data written to this register remains intact when the s1d13a05 is reset, as long as the chip is not powered off . bits 31-0 scratch pad c bits [31:0] this register contains general purpose read/write bits. these bits have no effect on hard- ware. note the contents of the scratch pad c register defaults to an un-defined state after initial power-up. any data written to this register remains intact when the s1d13a04 is reset, as long as the chip is not powered off . scratch pad a register reg[80h] default = not applicable read/write scratch pad a bits 31-24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 scratch pad a bits 15-0 1514131211109876543210 scratch pad b register reg[84h] default = not applicable read/write scratch pad b bits 31-24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 scratch pad b bits 15-0 1514131211109876543210 scratch pad c register reg[88h] default = not applicable read/write scratch pad c bits 31-24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 scratch pad c bits 15-0 1514131211109876543210 page 124 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 8.3.8 extended panel registers bits 8-0 cls pulse width bits [8:0] this register determines the width of the cls signal in pclks. note this register must be programmed such that the following formula is valid. (reg[a0h] bits 8-0) > 0 bits 5-0 ps1 rising edge bits [5:0] this register determines the number of pclks between the cls falling edge and the ps1 rising edge. bits 7-0 ps2 rising edge bits [7:0] this register determines the number of pclks between the lp falling edge and the first ps2 rising edge. note this register must be programmed such that the following formula is valid. (reg[a8h] bits 7-0) > 0 hr-tft cls width register reg[a0h] default = 0000012ch read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a cls pulse width bits 8-0 15 14 13 12 11 10 9876543210 hr-tft ps1 rising edge register reg[a4h] default = 00000032h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a ps1 rising edge bits 5-0 15 14 13 12 11 10 9 8 7 6543210 hr-tft ps2 rising edge register reg[a8h] default = 00000064h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a ps2 rising edge bits 7-0 15 14 13 12 11 10 9 876543210 epson research and development page 125 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 6-0 ps2 toggle width bits [6:0] this register determines the width of the ps2 signal before toggling (in number of pclks). note this register must be programmed such that the following formula is valid. (reg[ach] bits 6-0) > 0 bits 6-0 ps3 signal width bits [6:0] this register determines the width of the ps3 signal in pclks. note this register must be programmed such that the following formula is valid. (reg[b0h] bits 6-0) > 0 bits 4-0 rev toggle bits [4:0] this register determines the width in pclks to toggle the rev signal prior to lp rising edge. hr-tft ps2 toggle width register reg[ach] default = 0000000ah read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a ps2 toggle width bits 6-0 15 14 13 12 11 10 9 8 76543210 hr-tft ps3 signal width register reg[b0h] default = 00000064h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a ps3 signal width bits 6-0 15 14 13 12 11 10 9 8 76543210 hr-tft rev toggle point register reg[b4h] default = 0000000ah read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a rev toggle bits 4-0 15 14 13 12 11 10 9 8 7 6 543210 page 126 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 2-0 ps1/2 end bits [2:0] this register allows the ps signal to continue into the vertical non-display period (in lines). note this register must be programmed such that the following formula is valid. vt > (reg[b8h] bits 2-0) + vdp + vps + 1 bit 15 pol type this bit selects how often the pol signal is toggled. the s1d13a05 gpio2 pin controls the pol signal used for the tft type 2 interface. for all other panel interfaces this bit has no effect. when this bit = 0, the pol signal is toggled every line. when this bit = 1, the pol signal is toggled every frame. bits 13-11 ap pulse width bits [2:0] these bits specify the ap pulse width used for the tft type 2 interface. the s1d13a05 gpio1 pin controls the ap signal for the tft type 2 interface. for all other panel inter- faces it has no effect. hr-tft ps1/2 end register reg[b8h] default = 00000007h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a ps1/2 end bits 2-0 15 14 13 12 11 10 9 8 7 6 5 4 3210 type 2 tft configuration register reg[bch] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pol type n/a ap pulse width bits 2-0 n/a ap rising position bits 1-0 n/a vclk hold bits 1-0 n/a vclk setup bits 1-0 15 14 13 12 11 10 9 8 7 6 543 210 table 8-27: ap pulse width reg[4ch] bits 13-11 ap pulse width (in pclks) 000 20 001 40 010 80 011 120 100 150 101 190 110 240 111 270 epson research and development page 127 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 9-8 ap rising position bits [1:0] these bits specify the tft type 2 ac timing parameter from the rising edge of fpline (stb) to the rising edge of gpio1 (ap). the parameter is selected as follows. for all other panel interfaces it has no effect. bits 4-3 vclk hold bits [1:0] these bits specify the tft type 2 ac timing parameter from the rising edge of fpline (stb) to the falling edge of gpio0 (vclk). the parameter is selected as follows. for all other panel interfaces it has no effect. bits 1-0 vclk setup bits [1:0] these bits specify the tft type 2 ac timing parameter from the rising edge of gpio0 (vclk) to the rising edge of fpline (stb). the parameter is selected as follows. for all other panel interfaces it has no effect. table 8-28: ap rising position reg[4ch] bits 9-8 ap rising position (in pclks) 00 40 01 52 10 68 11 90 table 8-29: vclk hold reg[4ch] bits 4-3 vclk hold (in pclks) 00 7 01 9 10 12 11 16 table 8-30: vclk setup reg[4ch] bits 1-0 vclk setup (in pclks) 00 7 01 9 10 12 11 16 page 128 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 29-24 gpck rising edge to sth pulse bits[5:0] these bits determine the number of pclks from gpck rising edge to sth pulse. bits 22-16 gres falling edge to frp toggle point bits[6:0] these bits determine the number of pclks from gres falling edge to frp toggle point. bits 13-8 gres falling edge to gpck rising edge bits[5:0] these bits determine the number of pclks from gres falling edge to gpck rising edge. bits 5-0 gpck rising edge to gres rising edge bits[5:0] these bits determine the number of pclks from gpck rising edge to gres rising edge. bits 31-24 pol toggle position bits [7:0] these bits specify the toggle position of the pol signal in 2 pixel resolution. the s1d13a05 gpio2 pin controls the pol signal used for the tft type 3 interface. this register has no effect for all other panel interfaces. pol toggle position in pixels = (reg[d8h] bits 31-24) 2 bits 23-16 oe pulse width bits [7:0] these bits specify the pulse width of the oe signal in 2 pixel resolution. the s1d13a05 gpio1 pin controls the oe signal used for the tft type 3 interface. this register has no effect for all other panel interfaces. oe pulse width in pixels = (reg[d8h] bits 23-16) 2 bits 15-8 oe rising edge position bits [7:0] these bits specify the rising edge position of the oe signal in 2 pixel resolution. the s1d13a05 gpio1 pin controls the oe signal used for the tft type 3 interface. this reg- ister has no effect for all other panel interfaces. oe rising edge position in pixels = (reg[d8h] bits 15-8) 2 casio tft timing register reg[c0h] default = 09180e09h read/write n/a gpck rising edge to sth pulse bits 5-0 n/a gres falling edge to frp toggle point bits 6-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a gres falling edge to gpck rising edge bits 4-0 n/a gpck rising edge to gres rising edge bits 5-0 15 14 13 12 11 10 9 8 7 6543210 type 3 tft configuration register 0 reg[d8h] default = 00000000h read/write pol toggle position bits 7-0 oe pulse width bits 7-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 oe rising edge position bits 7-0 n/a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 epson research and development page 129 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 31-24 xoev end position bits [7:0] these bits specify the falling/rising edge position of the xoev signal in 2 pixel resolution (depending on the fpframe pulse polarity bit in reg[3ch] bit 23). the s1d13a05 gpo2 pin controls the xoev signal used for the tft type 3 interface. this register has no effect for all other panel interfaces. xoev falling edge position in pixels = (reg[dch] bits 31-24) 2 note if this register is set to 0, no pulse is generated. bits 23-16 xoev start position bits [7:0] these bits specify the rising/falling edge position of the xoev signal in 2 pixel resolution (depending on the fpframe pulse polarity bit in reg[3ch] bit 23). the s1d13a05 gpo2 pin controls the xoev signal used for the tft type 3 interface. this register has no effect for all other panel interfaces. xoev rising edge position in pixels = (reg[dch] bits 23-16) 2 note if this register is set to 0, no pulse is generated. bits 15-8 cpv pulse width bits [7:0] these bits specify the pulse width of the cpv signal in 2 pixel resolution. the s1d13a05 gpio0 pin controls the cpv signal used for the tft type 3 interface. this register has no effect for all other panel interfaces. cpv pulse width in pixels = (reg[dch] bits 15-8) 2 bits 7-0 vcom toggle position bits [7:0] these bits specify the toggle position of the vcom signal in 2 pixel resolution. the s1d13a05 gpo1 pin controls the vcom signal used for the tft type 3 interface. this register has no effect for all other panel interfaces. vcom toggle position in pixels = (reg[dch] bits 7-0) 2 type 3 tft configuration register 1 reg[dch] default = 00000000h read/write xoev end position bits 7-0 xoev start position bits 7-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cpv pulse width bits 6-0 vcom toggle position bits 7-0 1514131211109876543210 page 130 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 5-4 pclk2 divide rate bits [1:0] these bits specify the divide rate for pclk2. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 3-0 pclk1 divide rate bits [3:0] these bits specify the divide rate for pclk1. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. type 3 tft pclk divide register reg[e0h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a pclk2 divide rate bits 1-0 pclk1 divide rate bits 3-0 15 14 13 12 11 10 9 8 7 6543210 table 8-31: pclk2 divide rate reg[c8h] bits 5-4 pclk2 divide rate 00 64 01 128 10 256 11 512 table 8-32: pclk1 divide rate reg[c8h] bits 3-0 pclk1 divide rate 0000 2 0001 4 0010 8 0011 16 0100 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192 1101 16384 1110 32768 1111 65536 epson research and development page 131 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 13-8 partial mode display refresh cycle bits [5:0] these bits specify the refresh cycle for the partial mode display. the refresh cycle can be a value from 0 to 63. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bit 4 partial mode display enable this bit enables/disables the partial mode display for the tft type 3 and has no effect for all other panel interfaces. when this bit = 1, partial mode display is enabled. when this bit = 0, partial mode display is disabled. bit 3 partial mode display type select this bit selects the type of partial mode display. when this bit =0, the stripe type of partial mode display is selected. if stripe is enabled only the y position registers are used in calculating the partial display. when this bit = 1, type block type of partial mode display is selected. if block is enabled both the x and y position registers are used in calculating the partial display. bit 2 area 2 display enable this bit enables/disables the area 2 for partial mode display on the tft type 3 and has no effect for all other panel interfaces. when this bit = 1, area 2 is enabled. when this bit = 0, area 2 is disabled. bit 1 area 1 display enable this bit enables/disables the area 1 for partial mode display on the tft type 3 and has no effect for all other panel interfaces. when this bit = 1, area 1 is enabled. when this bit = 0, area 1 is disabled. bit 0 area 0 display enable this bit enables/disables the area 0 for partial mode display on the tft type 3 and has no effect for all other panel interfaces. when this bit = 1, area 0 is enabled. when this bit = 0, area 0 is disabled. type 3 tft partial mode display area control register reg[e4h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a partial mode display refresh cycle bits 5-0 n/a partial mode display enable partial mode display type select area 2 display enable area 1 display enable area 0 display enable 15 14 13 12 11 10 9 8 7 6 543210 page 132 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 29-24 partial area 0 y end position bits [5:0] these bits specify the y end position of partial area 0 in 8 line resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 21-16 partial area 0 x end position bits [5:0] these bits specify the x end position of partial area 0 in 8 pixel resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 13-8 partial area 0 y start position bits [5:0] these bits specify the y start position of partial area 0 in 8 line resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 5-0 partial area 0 x start position bits [5:0] these bits specify the x start position of partial area 0 in 8 pixel resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 29-24 partial area 1 y end position bits [5:0] these bits specify the y end position of partial area 1 in 8 line resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 21-16 partial area 1 x end position bits [5:0] these bits specify the x end position of partial area 1 in 8 pixel resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 13-8 partial area 1 y start position bits [5:0] these bits specify the y start position of partial area 1 in 8 line resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 5-0 partial area 1 x start position bits [5:0] these bits specify the x start position of partial area 1 in 8 pixel resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. type 3 tft partial area 0 positions register reg[e8h] default = 00000000h read/write n/a partial area 0 y e nd position bits 5-0 n/a partial area 0 x end position bits 5-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a partial area 0 y start position bits 5-0 n/a partial area 0 x start position bits 5-0 15 14 13 12 11 10 9 8 7 6543210 type 3 tft partial area 1 positions register reg[ech] default = 00000000h read/write n/a partial area 1 y e nd position bits 5-0 n/a partial area 1 x end position bits 5-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a partial area 1 y start position bits 5-0 n/a partial area 1 x start position bits 5-0 15 14 13 12 11 10 9 8 7 6543210 epson research and development page 133 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 29-24 partial area 2 y end position bits [5:0] these bits specify the y end position of partial area 2 in 8 line resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 21-16 partial area 2 x end position bits [5:0] these bits specify the x end position of partial area 2 in 8 pixel resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 13-8 partial area 2 y start position bits [5:0] these bits specify the y start position of partial area 2 in 8 line resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 5-0 partial area 2 x start position bits [5:0] these bits specify the x start position of partial area 2 in 8 pixel resolution. this register is used for the tft type 3 interface and has no effect for all other panel interfaces. bits 27-16 command 1 store bits [11:0] these bits store command 1 for the tft type 3 interface. this register has no effect for all other panel interfaces. bits 11-0 command 0 store bits [11:0] these bits store command 0 for the tft type 3 interface. this register has no effect for all other panel interfaces. type 3 tft partial area 2 positions register reg[f0h] default = 00000000h read/write n/a partial area 2 y end position bits 5-0 n/a partial area 2 x end position bits 5-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a partial area 2 y start position bits 5-0 n/a partial area 2 x start position bits 5-0 15 14 13 12 11 10 9 8 7 6543210 type 3 tft command store register reg[f4h] default = 00000000h read/write n/a command 1 store bits 11-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a command 0 store bits 11-0 15 14 13 1211109876543210 page 134 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 9-8 source driver ic number bits [1:0] these bits contain the number of source driver ics. bit 0 command send request after the cpu sets this bit, the s1d13a05 sends the command in the next non-display period and clears this bit automatically. this register has no effect for all other panel inter- faces. type 3 tft miscellaneous register reg[f8h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a source driver ic number bits 1-0 n/a command send request 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 table 8-33: number of source driver ics reg[e0h] bits 1-0 source driver ics 00 1 01 2 10 3 11 4 epson research and development page 135 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.4 usb registers (offset = 4000h) the s1d13a05 usb device occupies a 48 byte local register space which can be accessed by the cpu on the local host interface. to access the usb registers: 1. a valid usbclk must be provided. 2. the usbclk enable bit (reg[4000h] bit 7) must be set to 1 and the usb setup bit (reg[4000h] bit 2) must be set to 1. both bits should be set together. if any of the above conditions are not true, the usb registers must not be accessed. bit 7 usbclk enable. this bit allows the usbclk to be enabled/disabled allowing the s1d13a05 to save power when the usbclk is not required. the usbclk enable bit operates independently of the power save mode enable bit (reg[14h] bit 4). for example, enabling power save mode does not disable the usb section of the s1d13a05. it must be disabled using the usbclk enable bit. this bit should initially be set with the usb setup bit. however, it can be disabled/re- enabled individually. when this bit = 1, the usbclk is enabled. when this bit = 0, the usbclk is disabled. note the usb registers must not be accessed when this bit is 0. bit 6 software eot this bit determines the response to an in request to endpoint 4 when the transmit fifo is empty. if this bit is asserted, the s1d13a05 responds to an in request to endpoint 4 with an ack and a zero length packet if the fifo is empty. if this bit is not asserted, the s1d13a05 responds to an in request from endpoint 4 with an nak if the fifo is empty, indicating that it expects to transmit more data. this bit is automatically cleared when the s1d13a05 responds to the host with a zero length packet when the fifo is empty. control register reg[4000h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 usbclk enable software eot usb enable endpoint 4 stall endpoint 3 stall usb setup reserved reserved 76543210 page 136 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 5 usb enable any device or configuration descriptor reads from the host will be acknowledged with a nak until this bit is set. this allows time for the local cpu to set up the interrupt polling register, maximum packet size registers, and other configuration registers (e.g. product id and vendor id) before the host reads the descriptors. note as the device and configuration descriptors cannot be read by the host until the usb enable bit is set, the device enumeration process will not complete and the device will not be recognized on the usb. bit 4 endpoint 4 stall. if this bit is set, host bulk reads from the transmit fifo will result in a stall acknowl- edge by the s1d13a05. no data will be returned to the usb host. bit 3 endpoint 3 stall. if this bit is set, host bulk writes to the receive fifo will result in a stall acknowledge by the s1d13a05. receive data will be discarded. bit 2 usb setup this bit is used by software to select between gpio and usb functions for multifunction gpio pins (gpio[7:4]). this bit should be set at the same time as the usbclk enable bit. when this bit = 1, the usb function is selected. when this bit = 0, the gpio function is selected. note the usb registers must not be accessed when this bit is 0. bit 1 reserved. this bit must be set to 0. bit 0 reserved. this bit must be set to 0. bit 7 suspend request interrupt enable. when set, this bit enables an interrupt to occur when the usb host is requesting the s1d13a05 usb device to enter suspend mode. bit 6 sof interrupt enable. when set, this bit enables an interrupt to occur when a start-of-frame packet is received by the s1d13a05. bit 5 reserved. this bit must be set to 0. interrupt enable register 0 reg[4002h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 suspend request interrupt enable sof interrupt enable reserved endpoint 4 interrupt enable endpoint 3 interrupt enable endpoint 2 interrupt enable endpoint 1 interrupt enable n/a 7654321 0 epson research and development page 137 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 4 endpoint 4 interrupt enable. when set, this bit enables an interrupt to occur when a usb endpoint 4 data packet has been sent by the s1d13a05. bit 3 endpoint 3 interrupt enable. when set, this bit enables an interrupt to occur when a usb endpoint 3 data packet has been received by the s1d13a05. bit 2 endpoint 2 interrupt enable. when set, this bit enables an interrupt to occur when the usb endpoint 2 transmit mail- box registers have been read by the usb host. bit 1 endpoint 1 interrupt enable. when set, this bit enables an interrupt to occur when the usb endpoint 1 receive mail- box registers have been written to by the usb host. bit 7 suspend request interrupt status. this bit indicates when a suspend-request has been received by the s1d13a05. writing a 1 clears this bit. bit 6 sof interrupt status. this bit indicates when a start-of-frame packet has been received by the s1d13a05. writ- ing a 1 clears this bit. bit 5 reserved. this bit must be set to 0. bit 4 endpoint 4 interrupt status. this bit indicates when a usb endpoint 4 data packet has been sent by the s1d13a05. writing a 1 clears this bit. bit 3 endpoint 3 interrupt status (receive fifo valid). this bit indicates when a usb endpoint 3 data packet has been received by the s1d13a05. no more packets to endpoint 3 will be accepted until this bit is cleared. writ- ing a 1 clears this bit. bit 2 endpoint 2 interrupt status. this bit indicates when the usb endpoint 2 mailbox registers have been read by the usb host. writing a 1 clears this bit. bit 1 endpoint 1 interrupt status (receive mailbox valid). this bit indicates when the usb endpoint 1 mailbox registers have been written to by the usb host. writing a 1 clears this bit. bit 0 upper interrupt active (read only). at least one interrupt status bit is set in register reg[4008h]. interrupt status register 0 reg[4004h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 suspend request interrupt status sof interrupt status reserved endpoint 4 interrupt status endpoint 3 interrupt status endpoint 2 interrupt status endpoint 1 interrupt status upper interrupt active (read only) 76543210 page 138 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 1 transmit fifo almost empty interrupt enable. when set, this bit enables an interrupt to be generated when the transmit fifo almost empty status bit is set. note the transmit fifo almost empty threshold must be set greater than zero, as the fifo count must drop below the threshold to cause an interrupt. bit 0 receive fifo almost full interrupt enable. when set, this bit enables an interrupt to be generated when the receive fifo almost full status bit is set. note the receive fifo almost full threshold must be set less than 64, as the fifo count must rise above the threshold to cause an interrupt. bit 1 transmit fifo almost empty status. this bit is set when the number of bytes in the transmit fifo is equal to the transmit fifo almost empty threshold, and another byte is sent to the usb bus from the fifo. writing a 1 clears this bit. bit 0 receive fifo almost full status. this bit is set when the number of bytes in the receive fifo is equal to the receive fifo almost full threshold, and another byte is received from the usb bus into the fifo. writing a 1 clears this bit. interrupt enable register 1 reg[4006h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a transmit fifo almost empty interrupt enable receive fifo almost full interrupt enable 7 6 5 4 3 210 interrupt status register 1 reg[4008h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a transmit fifo almost empty status receive fifo almost full status 7 6 5 4 3 210 epson research and development page 139 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 2-0 endpoint 1 index register bits [2:0]. this register determines which endpoint 1 receive mailbox is accessed when the end- point 1 receive mailbox data register is read. this register is automatically incremented after the endpoint 1 receive mailbox data register is read. this index register wraps around to zero when it reaches the maximum count (7). bits 7-0 endpoint 1 receive mailbox data bits [7:0]. this register is used to read data from one of the receive mailbox registers. data is returned from the register selected by the endpoint 1 index register. the eight receive mailbox registers are written by a usb bulk transfer to endpoint 1, and can be used to pass messages from the usb host to the local cpu. the format and content of the messages are user defined. if enabled, usb writes to this register can generate an interrupt. bits 2-0 endpoint 2 index register bits [2:0]. this register determines which endpoint 2 transmit mailbox is accessed when the end- point 2 transmit mailbox data register is read or written. this register is automatically incremented after the endpoint 2 transmit mailbox data port is read or written. this index register wraps around to zero when it reaches the maximum count (7). endpoint 1 index register reg[4010h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a endpoint 1 index bits 2-0 (ro) 7 6 5 4 3210 endpoint 1 receive mailbox data register reg[4012h] default = 00h read only n/a 15 14 13 12 11 10 9 8 endpoint 1 receive mailbox data bits 7-0 76543210 endpoint 2 index register reg[4018h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a endpoint 2 index bits 2-0 7 6 5 4 3210 page 140 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 7-0 endpoint 2 transmit mailbox data bits [7:0]. this register is used to read or write one of the transmit mailbox registers. the register being accessed is selected by the endpoint 2 index register. the eight transmit mailbox registers are written by the local cpu and are read by a usb transfer from endpoint 2. the format and content of the messages are user defined. if enabled, usb reads from this reg- ister can generate an interrupt. bits 7-0 interrupt polling interval bits [7:0]. this register specifies the endpoint 2 interrupt polling interval in milliseconds. it can be read by the host through the endpoint 2 descriptor. bits7-0 endpoint 3 receive fifo data bits [7:0]. this register is used by the local cpu to read usb receive fifo data. the fifo data is written by the usb host using bulk or isochronous transfers to endpoint 3. bits 7-0 receive fifo count bits [7:0]. this register returns the number of receive fifo entries containing valid entries. values range from 0 (empty) to 64 (full). this register is automatically decremented after every read of the of the receive fifo data register (reg[4020h]). endpoint 2 transmit mailbox data register reg[401ah] default = 00h read/write n/a 15 14 13 12 11 10 9 8 endpoint 2 transmit mailbox data bits 7-0 76543210 endpoint 2 interrupt polling interval register reg[401ch] default = ffh read/write n/a 15 14 13 12 11 10 9 8 interrupt polling interval bits 7-0 76543210 endpoint 3 receive fifo data register reg[4020h] default = 00h read only n/a 15 14 13 12 11 10 9 8 endpoint 3 receive fifo data bits 7-0 76543210 endpoint 3 receive fifo count register reg[4022h] default = 00h read only n/a 15 14 13 12 11 10 9 8 receive fifo count bits 7-0 76543210 epson research and development page 141 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 4 receive fifo flush. writing to this bit causes the receive fifo to be flushed. reading this bit always returns a 0. bit 3 receive fifo overflow. if set, this bit indicates that an attempt was made by the usb host to write to the receive fifo when the receive fifo was full. writing a 1 clears this bit. bit 2 receive fifo underflow. if set, this bit indicates that an attempt was made to read the receive fifo when the receive fifo was empty. writing a 1 clears this bit. bit 1 receive fifo full. if set, this bit indicates that the receive fifo is full. bit 0 receive fifo empty. if set, this bit indicates that the receive fifo is empty. bits 7-0 endpoint 3 max packet size bits [7:0]. this register specifies the maximum packet size for endpoint 3 in units of 8 bytes (default = 64 bytes). it can be read by the host through the endpoint 3 descriptor. bits 7-0 transmit fifo data bits [7:0]. this register is used by the local cpu to write data to the transmit fifo. the fifo data is read by the usb host using bulk or isochronous transfers from endpoint 4. endpoint 3 receive fifo status register reg[4024h] default = 01h read/write n/a 15 14 13 12 11 10 9 8 n/a receive fifo flush receive fifo overflow receive fifo underflow receive fifo full (read only) receive fifo empty (read only) 7 6 543210 endpoint 3 maximum packet size register reg[4026h] default = 08h read/write n/a 15 14 13 12 11 10 9 8 endpoint 3 max packet size bits 7-0 76543210 endpoint 4 transmit fifo data register reg[4028h] default = 00h write only n/a 15 14 13 12 11 10 9 8 transmit fifo data bits 7-0 76543210 page 142 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 7-0 transmit fifo count bits [7:0]. this register returns the number of transmit fifo entries containing valid entries. values range from 0 (empty) to 64 (full). bit 5 transmit fifo valid. if set, this bit allows the data in the transmit fifo to be read by the next read from the host. this bit is automatically cleared by a host read. this bit is only used if bit 0 in usb[403ah] index [0ch] is set. bit 4 transmit fifo flush. writing to this bit causes the transmit fifo to be flushed. reading this bit always returns a 0. bit 3 transmit fifo overflow. if set, this bit indicates that an attempt was made by the local cpu to write to the transmit fifo when the transmit fifo was full. writing a 1 clears this bit. bit 2 reserved. bit 1 transmit fifo full (read only). if set, this bit indicates that the transmit fifo is full. bit 0 transmit fifo empty (read only). if set, this bit indicates that the transmit fifo is empty. bits 7-0 endpoint 4 max packet size bits [7:0]. this register specifies the maximum packet size for endpoint 4 in units of 8 bytes (default = 64 bytes). it can be read by the host through the endpoint 4 descriptor. endpoint 4 transmit fifo count register reg[402ah] default = 00h read only n/a 15 14 13 12 11 10 9 8 transmit fifo count bits 7-0 76543210 endpoint 4 transmit fifo status register reg[402ch] default = 01h read/write n/a 15 14 13 12 11 10 9 8 n/a transmit fifo valid transmit fifo flush transmit fifo overflow reserved transmit fifo full (read only) transmit fifo empty (read only) 7 6543210 endpoint 4 maximum packet size register reg[402eh] default = 08h read/write n/a 15 14 13 12 11 10 9 8 endpoint 4 max packet size bits 7-0 76543210 epson research and development page 143 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 7-0 chip revision bits [7:0]. this register returns current silicon revision number of the usb client. bit 7 suspend control if set, this bit indicates that there is a pending suspend request. writing a 1 clears this bit and causes the s1d13a05 usb device to enter suspended mode. bit 6 usb endpoint 4 stall the last usb in token could not be serviced because the endpoint was stalled (reg[4000h] bit 4 set), and was acknowledged with a stall. writing a 1 clears this bit. bit 5 usb endpoint 4 nak the last usb packet transmitted (in packet) encountered a fifo underrun condition, and was acknowledged with a nak. writing a 1 clears this bit. bit 4 usb endpoint 4 ack the last usb packet transmitted (in packet) was successfully acknowledged with an ack from the usb host. writing a 1 clears this bit. bit 3 usb endpoint 3 stall the last usb packet received (out packet) could not be accepted because the endpoint was stalled (reg[4000h] bit 3 set), and was acknowledged with a stall. writing a 1 clears this bit. bit 2 usb endpoint 3 nak the last usb packet received (out packet) could not be accepted, and was acknowl- edged with a nak. writing a 1 clears this bit. bit 1 usb endpoint 3 ack. the last usb packet received (out packet) was successfully acknowledged with an ack. writing a 1 clears this bit. bit 0 endpoint 2 valid. when this bit is set, the 8-byte endpoint 2 mailbox registers have been written by the local cpu, but not yet read by the usb host. the local cpu should not write into these regis- ters while this bit is set. revision register reg[4030h] default = 01h read only n/a 15 14 13 12 11 10 9 8 chip revision bits 7-0 76543210 usb status register reg[4032h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 suspend control usb endpoint 4 stall usb endpoint 4 nak usb endpoint 4 ack usb endpoint 3 stall usb endpoint 3 nak usb endpoint 3 ack endpoint 2 valid 76543210 page 144 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 10-0 frame counter bits [10:0] this register contains the frame counter from the most recent start-of-frame packet. bits 7-0 extended register index bits [7:0] this register selects which extended data register is accessed when the reg[403ah] is read or written. bits 7-0 extended data bits [7:0] this port provides access to one of the extended data registers. the index of the current register is held in reg[4038h]. frame counter msb register reg[4034h] default = 00h read only n/a 15 14 13 12 11 10 9 8 n/a frame counter bits 10-8 7 6 5 4 3210 frame counter lsb register reg[4036h] default = 00h read only n/a 15 14 13 12 11 10 9 8 frame counter bits 7-0 76543210 extended register index reg[4038h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 extended register index bits 7-0 76543210 extended register data reg[403ah] default = 04h read/write n/a 15 14 13 12 11 10 9 8 extended data bits 7-0 76543210 epson research and development page 145 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 15-0 vendor id bits [15:0] these registers determine the vendor id returned in a ?get device descriptor? request. bits 15-0 product id bits [15:0] these registers determine the product id returned in a ?get device descriptor? request. bits 15-0 release number bits [15:0] these registers determine the device release number returned in a ?get device descrip- tor? request. vendor id msb reg[403ah], index[00h] default = 04h read/write vendor id bits 15-8 76543210 vendor id lsb reg[403ah], index[01h] default = b8h read/write vendor id bits 7-0 76543210 product id msb reg[403ah], index[02h] default = 88h read/write product id bits 15-8 76543210 product id lsb reg[403ah], index[03h] default = 21h read/write product id bits 7-0 76543210 release number msb reg[403ah], index[04h] default = 01h read/write release number bits 15-8 76543210 release number lsb reg[403ah], index[05h] default = 00h read/write release number bits 7-0 76543210 page 146 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 5-0 receive fifo almost full threshold bits [5:0] this register determines the threshold at which the receive fifo almost full status bit is set. note the receive fifo almost full threshold must be set less than 64, as the fifo count must rise above the threshold to cause an interrupt. bits 5-0 transmit fifo almost empty threshold bits [5:0]. this register determines the threshold at which the transmit fifo almost empty status bit is set. note the transmit fifo almost empty threshold must be set greater than zero, as the fifo count must drop below the threshold to cause an interrupt. bit 0 usb string enable. when set, this bit allows the default vendor and product id string descriptors to be returned to the host. when this bit is cleared, the string index values in the device descriptor are set to zero. bits 7-0 maximum current bits [7:0]. the amount of current drawn by the peripheral from the usb port in increments of 2 ma. the s1d13a05 reports this value to the host controller in the configuration descriptor. the default and maximum value is 500 ma (fah * 2 ma). in order to comply with the usb specification the following formula must apply: reg[403ah] index[09h] fah. receive fifo almost full threshold reg[403ah], index[06h] default = 3ch read/write n/a receive fifo almost full threshold bits 5-0 7 6543210 transmit fifo almost empty threshold reg[403ah], index[07h] default = 04h read/write n/a transmit fifo almost empty threshold bits 5-0 7 6543210 usb control reg[403ah], index[08h] default = 01h read/write n/a usb string enable 7 6 5 4 3 2 10 maximum power consumption reg[403ah], index[09h] default = fah read/write maximum current bits 7-0 76543210 epson research and development page 147 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 7 ep4 data toggle bit. contains the value of the data toggle bit to be sent in response to the next in token to endpoint 4 from the usb host. note when a write is made to this bit, the value cannot be read back before a minimum of 12 usbclk. bit 6 ep3 data toggle bit. contains the value of the data toggle bit expected in the next data packet to endpoint 3 from the usb host. note when a write is made to this bit, the value cannot be read back before a minimum of 12 usbclk. bit 5 ep2 data toggle bit. contains the value of the data toggle bit to be sent in response to the next in token to endpoint 2 from the usb host. note when a write is made to this bit, the value cannot be read back before a minimum of 12 usbclk. bit 4 ep1 data toggle bit. contains the value of the data toggle bit expected in the next data packet to endpoint 1 from the usb host. note when a write is made to this bit, the value cannot be read back before a minimum of 12 usbclk. bit 3 reserved. this bit must be set to 0. bit 2 reserved. this bit must be set to 0. bit 0 reserved. this bit must be set to 0. packet control reg[403ah], index[0ah] default = 00h read/write ep4 data toggle ep3 data toggle ep2 data toggle ep1 data toggle reserved reserved n/a reserved 765432 10 page 148 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bit 0 reserved. this bit must be set to 0. bit 0 transmit fifo valid mode. when set, this bit causes a nak response to a host read request from the transmit fifo (ep4) unless the fifo valid bit (in register ep4stat) is set. when this bit is cleared, any data waiting in the transmit fifo will be sent in response to a host read request, and the fifo valid bit is ignored. these bits control inputs to the usb module. bit 6 uscmpen this bit controls the usb differential input receiver. 0 = differential input receiver disabled 1 = differential input receiver enabled bits 5 reserved. this bit must be set to 0. bits 4 reserved. this bit must be set to 0. bit 3 iso this bits selects between isochronous and bulk transfer modes for the fifos (endpoint 3 and endpoint 4). 0 = isochronous transfer mode 1 = bulk transfer mode bit 2 wakeup this active low bit initiates a usb remote wake-up. 0 = initiate usb remote wake-up 1 = no action reserved reg[403ah], index[0bh] default = 00h read/write n/a reserved 7 6 5 4 3 2 10 fifo control reg[403ah], index[0ch] default = 00h read/write n/a transmit fifo valid mode 7 6 5 4 3 2 10 usbfc input control register reg[4040h] default = 0dh read/write n/a 15 14 13 12 11 10 9 8 n/a uscmpen reserved reserved iso wakeup reserved reserved 76543210 epson research and development page 149 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 1 reserved. this bit must be set to 0. bit 0 reserved. this bit must be set to 0. these bits can generate interrupts. bit 1 usbdetect input pin status this read-only bit indicates the status of the usbdetect input pin after a steady-state period of 0.5 seconds. bit 0 usbpup output pin status this bit controls the state of the usbpup output pin. this bit must be set to 1 to enable the usb interface and usb registers. see the s1d13a05 programming notes and examples , document number x40-a-g-003-xx for further infor- mation on this bit. these bits enable interrupts from the corresponding bit of the interrupt control status/clear register 0. 0 = corresponding interrupt bit disabled (masked). 1 = corresponding interrupt bit enabled. reserved reg[4042h] n/a 15 14 13 12 11 10 9 8 n/a 7 6 5 4 3 2 1 0 pin input status / pin output data register reg[4044h] default = depends on usb input pin state read/write n/a 15 14 13 12 11 10 9 8 n/a usbdetect input pin status (read only) usbpup output pin status 7 6 5 4 3 210 interrupt control enable register 0 reg[4046h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a usb host connected reserved reserved reserved reserved usbreset reserved 76543210 page 150 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 these bits enable interrupts from the corresponding bit of the interrupt control status/clear register 1. 0 = corresponding interrupt bit disabled (masked). 1 = corresponding interrupt bit enabled. on reads, these bits represent the interrupt status for interrupts caused by low-to-high transitions on the corresponding signals. 0 (read) = no low-to-high event detected on the corresponding signal. 1 (read) = low-to-high event detected on the corresponding signal. on writes, these bits clear the corresponding interrupt status bit. 0 (write) = corresponding interrupt status bit unchanged. 1 (write) = corresponding interrupt status bit cleared to zero. these bits must always be cleared via a write to this register before first use. this will ensure that any changes on input pins during system initialization do not generate erroneous interrupts. the interrupt bits are used as follows. bit 6 usb host connected indicates the usb device is connected to a usb host. bit 5 reserved. must be set to 0. bit 4 reserved. must be set to 0. bit 3 reserved. must be set to 0. bit 2 reserved. must be set to 0. bit 1 usbreset indicates the usb device is reset using the reset# pin or using the usb port reset. interrupt control enable register 1 reg[4048h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a usb host disconnect reserved device configured reserved reserved reserved int 76543210 interrupt control status/clear register 0 reg[404ah] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a usb host connected reserved reserved reserved reserved usbreset reserved 76543210 epson research and development page 151 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 0 reserved. must be set to 0. on reads, these bits represent the interrupt status for interrupts caused by high-to-low transitions on the corresponding signals. 0 (read) = no high-to-low event detected on the corresponding signal. 1 (read) = high-to-low event detected on the corresponding signal. on writes, these bits clear the corresponding interrupt status bit. 0 (write) = corresponding interrupt status bit unchanged. 1 (write) = corresponding interrupt status bit cleared to zero. these bits must always be cleared via a write to this register before first use. this will ensure that any changes on input pins during system initialization do not generate erroneous interrupts. the interrupt bits are used as follows. bit 6 usb host disconnected indicates the usb device is disconnected from a usb host. bit 5 reserved. must be set to 0. bit 4 device configured. indicates the usb device has been configured by the usb host. bit 3 reserved. must be set to 0. bit 2 reserved. must be set to 0. bit 1 reserved. must be set to 0. bit 0 int indicates an interrupt request originating from within the usb registers (reg[4000h] to reg[403ah]). interrupt control status/clear register 1 reg[404ch] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a usb host disconnected reserved device configured reserved reserved reserved int 76543210 page 152 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 these read-only bits represent the logical and of the corresponding interrupt control status/clear register 0 (reg[404ah])and the interrupt control enable register 0 (reg[4046h]). these read-only bits represent the logical and of the corresponding interrupt control status/clear register 1 (reg[404ch]) and the interrupt control enable register 1 (reg[4048h]). bits 7-0 usb software reset bits [7:0] (write only) when the specific code of 10100100b is written to these bits the usb module of the s1d13a05 is reset. use of the above code avoids the possibility of accidently resetting the usb. bits 1-0 usb wait state bits [1:0] this register controls the number of wait states the s1d13a05 uses for its internal usb support. for all bus interfaces supported by the s1d13a05 these bits must be set to 01 . interrupt control masked status register 0 reg[404eh] default = 00h read only n/a 15 14 13 12 11 10 9 8 n/a usb host connected reserved reserved reserved reserved usbreset reserved 76543210 interrupt control masked status register 1 reg[4050h] default = 00h read only n/a 15 14 13 12 11 10 9 8 n/a usb host disconnected reserved device configured reserved reserved reserved int 76543210 usb software reset register reg[4052h] default = 00h write only n/a 15 14 13 12 11 10 9 8 usb software reset (code = 10100100) bits 7-0 76543210 usb wait state register reg[4054h] default = 00h read/write n/a 15 14 13 12 11 10 9 8 n/a usb wait state bits 1-0 7 6 5 4 3 210 epson research and development page 153 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8.5 2d acceleration (bitblt) registers (offset = 8000h) these registers control the s1d13a05 2d acceleration engine. for detailed bitblt programming instructions, see the s1d13a05 programming notes and examples , document number x40a-g-003-xx. bit 18 bitblt color format select this bit selects the color format that the 2d operation is applied to. when this bit = 0, 8 bpp (256 color) format is selected. when this bit = 1, 16 bpp (64k color) format is selected. bit 17 bitblt destination linear select when this bit = 1, the destination bitblt is stored as a contiguous linear block of memory. when this bit = 0, the destination bitblt is stored as a rectangular region of memory. the bitblt memory address offset register (reg[8014h]) determines the address offset from the start of one line to the next line. bit 16 bitblt source linear select when this bit = 1, the source bitblt is stored as a contiguous linear block of memory. when this bit = 0, the source bitblt is stored as a rectangular region of memory. the bitblt memory address offset register (reg[8014h]) determines the address offset from the start of one line to the next line. bit 0 bitblt enable this bit is write only. setting this bit to 1 begins the 2d bitblt operation. this bit must not be set to 0 while a bitblt operation is in progress. note to determine the status of a bitblt operation use the bitblt busy status bit (reg[8004h] bit 0). bitblt control register reg[8000h] default = 00000000h read/write n/a color format select dest linear select source linear select 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a bitblt enable (wo) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 page 154 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 28-24 number of used fifo entries bits [4:0] these bits indicate the minimum number of fifo entries currently in use (there may be more values in internal pipeline stages). bits 20-16 number of free fifo entries bits [4:0] these bits indicate the number of empty fifo entries available. if these bits return a 0, the fifo is full. bit 6 bitblt fifo not-empty status this is a read-only status bit. when this bit = 0, the bitblt fifo is empty. when this bit = 1, the bitblt fifo has at least one data. to reduce system memory read latency, software can monitor this bit prior to a bitblt read burst operation. the following table shows the number of words available in bitblt fifo under different status conditions. bit 5 bitblt fifo half full status this is a read-only status bit. when this bit = 1, the bitblt fifo is half full or greater than half full. when this bit = 0, the bitblt fifo is less than half full. bit 4 bitblt fifo full status this is a read-only status bit. when this bit = 1, the bitblt fifo is full. when this bit = 0, the bitblt fifo is not full. bitblt status register reg[8004h] default = 00000000h read only n/a number of used fifo entries n/a number of free fifo entries (0 means full) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a fifo not empty fifo half full fifo full status n/a bitblt busy status 15 14 13 12 11 10 9 8 7654 3 2 10 table 8-34: bitblt fifo words available bitblt fifo full status (reg[8004h] bit 4) bitblt fifo half full status (reg[8004h] bit 5) bitblt fifo not empty status (reg[8004h] bit 6) number of words available in bitblt fifo 0000 0 0 1 1 to 6 0 1 1 7 to 14 11115 to 16 epson research and development page 155 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bit 0 bitblt busy status this bit is a read-only status bit. when this bit = 1, the bitblt operation is in progress. when this bit = 0, the bitblt operation is complete. note during a bitblt read operation, the bitblt engine does not attempt to keep the fifo full. if the fifo becomes full, the bitblt operation stops temporarily as data is read out of the fifo. the bitblt will restart only when less than 14 values remain in the fifo. bits 19-16 bitblt raster operation code/color expansion bits [3:0] rop code for write bitblt and move bitblt. bits 2-0 also specify the start bit position for color expansion. note s = source, d = destination, p = pattern. ~ = not, . = logical and, + = logical or, ^ = logical xor bitblt command register reg[8008h] default = 00000000h read/write n/a bitblt rop code bits 3-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a bitblt operation bits 3-0 15 14 13 12 11 10 9 8 7 6 5 43210 table 8-35 : bitblt rop code/color expansion function selection bitblt rop code bits [3:0] boolean function for write bitblt and move bitblt boolean function for pattern fill start bit position for color expansion 0000 0 (blackness) 0 (blackness) bit 0 0001 ~s . ~d or ~(s + d) ~p . ~d or ~(p + d) bit 1 0010 ~s . d ~p . d bit 2 0011 ~s ~p bit 3 0100 s . ~d p . ~d bit 4 0101 ~d ~d bit 5 0110 s ^ d p ^ d bit 6 0111 ~s + ~d or ~(s . d) ~p + ~d or ~(p . d) bit 7 1000 s . d p . d bit 0 1001 ~(s ^ d) ~(p ^ d) bit 1 1010 d d bit 2 1011 ~s + d ~p + d bit 3 1100 s p bit 4 1101 s + ~d p + ~d bit 5 1110 s + d p + d bit 6 1111 1 (whiteness) 1 (whiteness) bit 7 page 156 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 3-0 bitblt operation bits [3:0] specifies the 2d operation to be carried out based on the following table. table 8-36 : bitblt operation selection bitblt operation bits [3:0] bitblt operation 0000 write bitblt with rop. 0001 read bitblt. 0010 move bitblt in positive direction with rop. 0011 move bitblt in negative direction with rop. 0100 transparent write bitblt. 0101 transparent move bitblt in positive direction. 0110 pattern fill with rop. 0111 pattern fill with transparency. 1000 color expansion. 1001 color expansion with transparency. 1010 move bitblt with color expansion. 1011 move bitblt with color expansion and transparency. 1100 solid fill. other combinations reserved epson research and development page 157 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 20-0 bitblt source start address bits [20:0] a 21-bit register that specifies the source start address for the bitblt operation. if data is sourced from the cpu, then bit 0 is used for byte alignment within a 16-bit word and the other address bits are ignored. in pattern fill operation, the bitblt source start address is defined by the following equation. value programmed to the source start address register = pattern base address + pattern line offset + pixel offset. the following table shows how source start address register is defined for 8 and 16 bpp color depths. note for further information on the bitblt source start address register, see the s1d13a05 programming notes and examples , document number x40a-g-003-xx. bits 20-0 bitblt destination start address bits [20:0] a 21-bit register that specifies the destination start address for the bitblt operation. bitblt source start address register reg[800ch] default = 00000000h read/write n/a bitblt source start address bits 20-16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bitblt source start address bits 15-0 15141312111098765432 1 0 table 8-37 : bitblt source start address selection color format pattern base address[20:0] pattern line offset[2:0] pixel offset[3:0] 8 bpp bitblt source start address[20:6] bitblt source start address[5:3] bitblt source start address[2:0] 16 bpp bitblt source start address[20:7] bitblt source start address[6:4] bitblt source start address[3:0] bitblt destination start address register reg[8010h] default = 00000000h read/write n/a bitblt destination start address bits 20-16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bitblt destination start address bits 15-0 15141312111098765432 1 0 page 158 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 bits 10-0 bitblt memory address offset bits [10:0] these bits are the display?s 11-bit address offset from the starting word of line n to the starting word of line n + 1 . they are used only for address calculation when the bitblt is configured as a rectangular region of memory. they are not used for the displays. bits 9-0 bitblt width bits [9:0] a 10-bit register that specifies the bitblt width in pixels - 1. bitblt width in pixels = (reg[8018h] bits 9-0) + 1 bits 9-0 bitblt height bits [9:0] a 10-bit register that specifies the bitblt height in lines - 1. bitblt height in lines = (reg[801ch] bits 9-0) + 1 bitblt memory address offset register reg[8014h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a bitblt memory address offset bits 10-0 15 14 13 12 111098765432 1 0 bitblt width register reg[8018h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a bitblt width bits 9-0 15 14 13 12 11 1098765432 1 0 bitblt height register reg[801ch] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n/a bitblt height bits 9-0 15 14 13 12 11 1098765432 1 0 epson research and development page 159 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 bits 15-0 bitblt background color bits [15:0] this register specifies the bitblt background color for color expansion or key color for transparent bitblt. for 16 bpp color depths (reg[8000h] bit 18 = 1), bits 15-0 are used. for 8 bpp color depths (reg[8000h] bit 18 = 0), bits 7-0 are used. bits 15-0 bitblt foreground color bits [15:0] this register specifies the bitblt foreground color for color expansion or solid fill. for 16 bpp color depths (reg[8000h] bit 18 = 1), bits 15-0 are used. for 8 bpp color depths (reg[8000h] bit 18 = 0), bits 7-0 are used. bitblt background color register reg[8020h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bitblt background color bits 15-0 15141312111098765432 1 0 bitblt foreground color register reg[8024h] default = 00000000h read/write n/a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bitblt foreground color bits 15-0 15141312111098765432 1 0 page 160 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 8.6 2d accelerator (bitblt) data register descriptions the 2d accelerator (bitblt) data registers decode ab15-ab0 and require ab16 = 1. the bitblt data registers are 32-bit wide. byte access to the bitblt data registers is not allowed. bits 15-0 bitblt data bits [15:0] this register specifies the bitblt data. this register is loosely decoded from 10000h to 1fffeh. 2d accelerator (bitblt) data memory mapped region register ab16-ab0 = 10000h-1fffeh, even addresses read/write bitblt data bits 31-16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bitblt data bits 15-0 1514131211109876543210 epson research and development page 161 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 9 2d accelerator (bitblt) engine 9.1 overview the s1d13a05 is designed with a built-in 2d bitblt engine which increases the perfor- mance of bit block transfers (bitblt). it supports 8 and 16 bit-per-pixel color depths. the bitblt engine supports rectangular and linear addressing modes for source and desti- nation in a positive direction for all bitblt operations except the move bitblt which also supports in a negative direction. the bitblt operations support byte alignment of all types. the bitblt engine has a dedicated bitblt io access space. this allows the bitblt engine to support simultaneous bitblt and host side operations. 9.2 bitblt operations the s1d13a05 2d bitblt engine supports the following bitblts. for detailed infor- mation on using the individual bitblt operations, refer to the s1d13a05 programming notes and examples, document number x40a-g-003-xx. ? write bitblt. ? move bitblt. ? solid fill bitblt. ? pattern fill bitblt. ? transparent write bitblt. ? transparent move bitblt. ? read bitblt. ? color expansion bitblt. ? move bitblt with color expansion. note for details on the bitblt registers, see section 8.5, ?2d acceleration (bitblt) regis- ters (offset = 8000h)? on page 153. page 162 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 10 frame rate calculation the following formula is used to calculate the display frame rate. where: f pclk = pclk frequency (hz) ht = horizontal total = ((reg[20h] bits 6-0) + 1) x 8 pixels vt = vertical total = ((reg[30h] bits 9-0) + 1) lines framerate f pclk ht () vt () -------------------------------- = epson research and development page 163 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 11 display data formats the following diagrams show the display mode data formats for a little-endian system. figure 11-1: 4/8/16 bit-per-pixel display data memory organization note 1. the host-to-display mapping shown here is for a little endian system. 2. for 16 bpp format, r n , g n , b n represent the red, green, and blue color components. 4 bpp: a 0 b 0 c 0 d 0 a 1 b 1 c 1 d 1 host address display memory a 2 b 2 c 2 d 2 a 3 b 3 c 3 d 3 bit 7 bit 0 a 4 b 4 c 4 d 4 a 5 b 5 c 5 d 5 host address display memory bit 7 bit 0 8 bpp: a 0 b 0 c 0 d 0 e 0 f 0 g 0 h 0 a 1 b 1 c 1 d 1 e 1 f 1 g 1 h 1 a 2 b 2 c 2 d 2 e 2 f 2 g 2 h 2 byte 0 byte 1 byte 2 byte 0 byte 1 byte 2 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 (a n , b n , c n , d n , e n , f n , g n , h n ) 16 bpp: r 0 4 host address display buffer bit 7 bit 0 r 0 3 r 0 2 r 0 1 r 0 0 g 0 5 g 0 4 g 0 3 g 0 2 g 0 1 g 0 0 b 0 4 b 0 3 b 0 2 b 0 1 b 0 0 r 1 4 r 1 3 r 1 2 r 1 1 r 1 0 g 1 5 g 1 4 g 1 3 g 1 2 g 1 1 g 1 0 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 5-6-5 rgb byte 0 byte 1 byte 2 byte 3 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 p n = (r n 4-0 , g n 5-0 , b n 4-0 ) 2 bpp: a 0 b 0 a 1 b 1 a 2 b 2 a 3 b 3 host address display memory a 4 b 4 a 5 b 5 a 6 b 6 a 7 b 7 bit 7 bit 0 a 8 b 8 a 9 b 9 a 10 b 10 a 11 b 11 byte 0 byte 1 byte 2 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 1 bpp: a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 host address display memory a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 bit 7 bit 0 a 16 a 17 a 18 a 19 a 20 a 21 a 22 a 23 byte 0 byte 1 byte 2 panel display p 0 p 1 p 2 p 3 p 4 p 5 p 6 p 7 lut lut lut lut bypasses lut p n = rgb value from lut index (a n , b n , c n , d n ) p n = rgb value from lut index (a n , b n ) p n = rgb value from lut index (a n ) p n = rgb value from lut index page 164 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 12 look-up table architecture the following figures are intended to show the display data output path only. note when video data invert is enabled the video data is inverted after the look-up table. 12.1 monochrome modes the green look-up table (lut) is used for all monochrome modes. 1 bit-per-pixel monochrome mode figure 12-1: 1 bit-per-pixel monochrome mode data output path 2 bit-per-pixel monochrome mode figure 12-2: 2 bit-per-pixel monochrome mode data output path green look-up table 256x6 00 01 1 bit-per-pixel data 6-bit gray data from display buffer = unused look-up table entries 00 01 fc fd fe ff green look-up table 256x6 00 01 2 bit-per-pixel data 6-bit gray data from display buffer 10 11 = unused look-up table entries 00 01 02 03 fc fd fe ff epson research and development page 165 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 4 bit-per-pixel monochrome mode figure 12-3: 4 bit-per-pixel monochrome mode data output path 8 bit-per-pixel monochrome mode figure 12-4: 8 bit-per-pixel monochrome mode data output path green look-up table 256x6 0000 0001 4 bit-per-pixel data 6-bit gray data from display buffer 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 = unused look-up table entries 00 01 02 03 fc fd fe ff 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0000 0000 0000 0001 6-bit gray data 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 green look-up table 256x6 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff 8 bit-per-pixel data from display buffer page 166 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 16 bit-per-pixel monochrome mode the lut is bypassed and the green data is directly mapped for this color depth? ?display data formats? on page 163.. 12.2 color modes 1 bit-per-pixel color figure 12-5: 1 bit-per-pixel color mode data output path 1 bit-per-pixel data from image buffer 6-bit blue data 0 1 blue look-up table 256x6 00 01 fc fd fe ff 6-bit red data 0 1 red look-up table 256x6 00 01 fc fd fe ff 6-bit green data 0 1 green look-up table 256x6 00 01 fc fd fe ff = unused look-up table entries epson research and development page 167 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 2 bit-per-pixel color figure 12-6: 2 bit-per-pixel color mode data output path 2 bit-per-pixel data from image buffer 6-bit blue data 00 01 10 11 blue look-up table 256x6 00 01 02 03 fc fd fe ff 6-bit red data 00 01 10 11 red look-up table 256x6 00 01 02 03 fc fd fe ff 6-bit green data 00 01 10 11 green look-up table 256x6 00 01 02 03 fc fd fe ff = unused look-up table entries page 168 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 4 bit-per-pixel color figure 12-7: 4 bit-per-pixel color mode data output path 0000 0001 4 bit-per-pixel data 6-bit red data from image buffer 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 6-bit green data 6-bit blue data red look-up table 256x6 00 01 02 03 fc fd fe ff 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 green look-up table 256x6 00 01 02 03 fc fd fe ff 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 blue look-up table 256x6 00 01 02 03 fc fd fe ff 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f = unused look-up table entries epson research and development page 169 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 8 bit-per-pixel color mode figure 12-8: 8 bit-per-pixel color mode data output path 16 bit-per-pixel color mode the lut is bypassed and the color data is directly mapped for this color depth? ?display data formats? on page 163. red look-up table 256x6 00 01 02 03 0000 0000 0000 0001 8 bit-per-pixel data 6-bit red data from display buffer 0000 0010 0000 0011 04 05 06 07 0000 0100 0000 0101 0000 0110 0000 0111 f8 f9 fa fb fc fd fe ff 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 0000 0000 0000 0001 6-bit green data 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 0000 0000 0000 0001 6-bit blue data 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 green look-up table 256x6 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff blue look-up table 256x6 00 01 02 03 04 05 06 07 f8 f9 fa fb fc fd fe ff page 170 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 13 swivelview? 13.1 concept most computer displays are refreshed in landscape orientation ? from left to right and top to bottom. computer images are stored in the same manner. swivelview? is designed to rotate the displayed image on an lcd by 90 , 180 , or 270 in a counter-clockwise direction . the rotation is done in hardware and is transparent to the user for all display buffer reads and writes. by processing the rotation in hardware, swivelview? offers a performance advantage over software rotation of the displayed image. the image is not actually rotated in the display buffer since there is no address translation during cpu read/write. the image is rotated during display refresh. 13.2 90 swivelview? 90 swivelview? requires the memory clock (mclk) to be at least 1.25 times the frequency of the pixel clock (pclk), i.e. mclk 1.25pclk. the following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. the application image is written to the s1d13a05 in the following sense: a?b?c?d. the display is refreshed by the s1d13a05 in the following sense: b-d-a-c. figure 13-1: relationship between the screen image and the image refreshed in 90 swivelview. image seen by programmer = image in display buffer 480 swivelview window 480 320 ab c d d c b a 320 swivelview window display start address image refreshed by s1d13a05 (panel origin) physical memory start address epson research and development page 171 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 13.2.1 register programming enable 90 swivelview? mode set swivelview? mode select bits (reg[10h] bits 17:16) to 01. display start address the display refresh circuitry starts at pixel ?b?, therefore the main window display start address register (reg[40h]) must be programmed with the address of pixel ?b?. to calculate the value of the address of pixel ?b? use the following formula (assumes 8 bpp color depth). reg[40h] bits 16:0 = ((image address + (panel height x bpp 8)) 4) - 1 = ((0 + (320 pixels x 8 bpp 8)) 4) -1 = 79 (4fh) line address offset the main window line address offset register (reg[44h]) is based on the display width and programmed using the following formula. reg[44h] bits 9:0 = display width in pixels (32 bpp) = 320 pixels 32 8 bpp = 80 (50h) page 172 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 13.3 180 swivelview? the following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. the application image is written to the s1d13a05 in the following sense: a?b?c?d. the display is refreshed by the s1d13a05 in the following sense: d-c-b-a. figure 13-2: relationship between the screen image and the image refreshed in 180 swivelview. 13.3.1 register programming enable 180 swivelview? mode set swivelview? mode select bits (reg[10h] bits 17:16) to 10. display start address the display refresh circuitry starts at pixel ?d?, therefore the main window display start address register (reg[40h]) must be programmed with the address of pixel ?d?. to calculate the value of the address of pixel ?d? use the following formula (assumes 8 bpp color depth). reg[40h] bits 16:0 = ((image address + (offset x (panel height - 1) + panel width) x bpp 8) 4) - 1 = ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp 8) 4) - 1 = 38399 (95ffh) image seen by programmer = image in display buffer 480 swivelview window 480 320 ab cd 320 image refreshed by s1d13a05 swivelview window ab cd display start address (panel origin) physical memory start address epson research and development page 173 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 line address offset the main window line address offset register (reg[44h]) is based on the display width and programmed using the following formula. reg[44h] bits 9:0 = display width in pixels (32 bpp) = 480 pixels 32 8 bpp = 120 (78h) 13.4 270 swivelview? 270 swivelview? requires the memory clock (mclk) to be at least 1.25 times the frequency of the pixel clock (pclk), i.e. mclk 1.25pclk. the following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. the application image is written to the s1d13a05 in the following sense: a?b?c?d. the display is refreshed by the s1d13a05 in the following sense: c-a-d-b. figure 13-3: relationship between the screen image and the image refreshed in 270 swivelview. image seen by programmer = image in display buffer 480 swivelview window 480 320 ab c d d c b a 320 swivelview window image refreshed by s1d13a05 physical memory display start address (panel origin) start address page 174 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 13.4.1 register programming enable 270 swivelview? mode set swivelview? mode select bits (reg[10h] bits 17:16) to 11. display start address the display refresh circuitry starts at pixel ?c?, therefore the main window display start address register (reg[40h]) must be programmed with the address of pixel ?c?. to calculate the value of the address of pixel ?c? use the following formula (assumes 8 bpp color depth). reg[40h] bits 16:0 = (image address + ((panel width - 1) x offset x bpp 8) 4) = (0 + ((480 pixels - 1) x 320 pixels x 8 bpp 8) 4) = 38320 (95b0h) line address offset the main window line address offset register (reg[44h]) is based on the display width and programmed using the following formula. reg[44h] bits 9:0 = display width in pixels (32 bpp) = 320 pixels 32 8 bpp = 80 (50h) epson research and development page 175 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 14 picture-in-picture plus (pip + ) 14.1 concept picture-in-picture plus (pip + ) enables a secondary window (or pip + window) within the main display window. the pip + window may be positioned anywhere within the virtual display and is controlled through the pip + window control registers (reg[50h] through reg[5ch]). the pip + window retains the same color depth and swivelview orientation as the main window. the following diagram shows an example of a pip + window within a main window and the registers used to position it. figure 14-1: picture-in-picture plus with swivelview disabled pip + window main-window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position 0 swivelview tm (reg[58h] bits 9-0) (reg[58h] bits 25-16) (reg[5ch] bits 25-16) (reg[5ch] bits 9-0) page 176 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 14.2 with swivelview enabled 14.2.1 swivelview 90 figure 14-2: picture-in-picture plus with swivelview 90 enabled 14.2.2 swivelview 180 figure 14-3: picture-in-picture plus with swivelview 180 enabled pip + window main-window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position 90 swivelview tm (reg[58h] bits 25-16) (reg[58h] bits 9-0) (reg[5ch] bits 9-0) (reg[5ch] bits 25-16) pip + window main-window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position 180 swivelview tm (reg[58h] bits 25-16) (reg[58h] bits 9-0) (reg[5ch] bits 25-16) (reg[5ch] bits 9-0) epson research and development page 177 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 14.2.3 swivelview 270 figure 14-4: picture-in-picture plus with swivelview 270 enabled pip + window main-window pip + window y start position panel?s origin pip + window y end position pip + window x start position pip + window x end position 270 swivelview tm (reg[58h] bits 25-16) (reg[5ch] bits 25-16) (reg[5ch] bits 9-0) (reg[58h] bits 9-0) page 178 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 15 power save mode a software initiated power save mode is incorporated into the s1d13a05 to accommodate the need for power reduction in the hand-held devices market. this mode is enable via the power save mode enable bit (reg[14h] bit 4). software power save mode saves power by powering down the control signals and stopping display refresh accesses to the display buffer. for programming information on disabling the clocks, see the s1d13a05 programming notes and examples , document number x40a-g-003-xx. note 1 when power save mode is enabled, the memory controller is powered down and the status of the memory controller is indicated by the memory controller power save sta- tus bit (reg[14h] bit 6). however, memory reads/writes are possible during power save mode because the s1d13a05 dynamically enables the memory controller for display buffer accesses. 2 gpios can be accessed and if configured as outputs can be changed. 3 the power-down state of the usb section is controlled by the usbclk enable bit (reg[4000h] bit 7). after reset, the s1d13a05 is always in power save mode. software must initialize the chip (i.e. programs all registers) and then clear the power save mode enable bit. table 15-1: power save mode function summary software power save normal io access possible? yes yes memory access possible? yes 1 yes look-up table registers access possible? yes yes display active? no yes lcd i/f outputs forced low active pwmclk stopped active gpio pins configured for hr-tft forced low active gpio pins configured as gpios; access possible? yes 2 yes usb running? yes 3 yes epson research and development page 179 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 16 usb considerations 16.1 usb oscillator circuit the following circuit provides an example implementation for using an external oscillator to drive usbclk. figure 16-1: usb oscillator example circuit the following values are recommended for a 48mhz fundamental mode oscillator. if an oscillator of a different value is used, the capacitive and resistive values must be adjusted accordingly. table 16-1: resistance and capacitance values for example circuit symbol value r f 1m r d 470 c g 12pf c d 12pf usbosci usbosco r f r d c g c d page 180 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 17 mechanical data figure 17-1: mechanical data pfbga 121-pin package all dimensions in mm 10 1.2max 0.05max top view l k j h g f e d c b a 12345678910 11 0.8 1.0 0.45 bottom view 0.08 m side view 1.0 -0.15 +0.30 10 -0.15 +0.30 0.35 -0.05 +0.10 0.1max -0.05 +0.10 epson research and development page 181 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 18 references the following documents contain additional information related to the s1d13a05. document numbers are listed in parenthesis after the document name. all documents can be found at the epson research and development website at www.erd.epson.com . ? s1d13a05 product brief (x40a-c-001-xx) ? s1d13a05 programming notes and examples (x40a-g-003-xx) ? s1d13a05 register summary (x40a-r-001-xx) ? interfacing to the toshiba tmpr3905/3912 microprocessor (x40a-g-002-xx) ? interfacing to the pc card bus (x40a-g-005-xx) ? s1d13a05 power consumption (x40a-g-006-xx) ? interfacing to the freescale mcf5307 "coldfire" microprocessor (x40a-g-010-xx) ? s1d13a05 wind river windml v2.0 display drivers (x40a-e-003-xx) ? s5u13a05b00c rev. 1.0 evaluation board user manual (x40a-g-004-xx) ? 13a05cfg configuration utility users manual (x40a-b-001-xx) ? 13a05play diagnostic utility users manual (x40a-b-002-xx) ? 13a05view demonstration utility users manual (x40a-b-003-xx) ? s5u13a05p00c100 evaluation board user manual (x40a-g-014-xx) ? errata no. x00z-p-001 (x00z-p-001-xx) page 182 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 19 sales and technical support america epson electronics america, inc. 214 devcon drive san jose, ca 95112,usa phone: +1-800-228-3964 fax: +1-408-922-0238 europe epson europe electronics gmbh riesstrasse 15, 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 asia epson (china) co., ltd. 7f, jinbao bldg., no.89 jinbao st., beijing 100005, china phone: +86-10-8522-1199 fax: +86-10-8522-1125 shanghai branch 7f, block b, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5577 fax: +86-21-5423-4677 epson hong kong ltd. unit 715-723, 7/f trade square, 681 cheung sha wan road, kowloon, hong kong phone: +852-2585-4600 fax: +852-2827-4346 shenzhen branch 12f, dawning mansion, keji south 12th road, hi-tech park, shenzhen 518057, china phone: +86-755-2699-3828 fax: +86-755-2699-3838 epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110, taiwan phone: +886-2-8786-6688 fax: +886-2-8786-6660 epson singapore pte., ltd. 1 harbourfront place, #03-02 harbourfront tower one, singapore 098633 phone: +65-6586-5500 fax: +65-6271-3182 seiko epson corp. korea office 5f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 seiko epson corp. microdevices operations division device sales & marketing dept. 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 dongcheng district, epson research and development page 183 vancouver design center hardware functional specification s1d13a05 issue date: 2012/02/27 x40a-a-001-07 revision 7.7 change record x40a-a-001-07 revision 7.7- issued: february 27, 2012 ? globally remove qfp5-128 package ? section 2.9, remove qfp package to features ? section 4.1.2, remove qfp package pin diagram ? section 4.2, remove qfp package pin descriptions ? section 18, remove qfp package mechanical drawing x40a-a-001-07 revision 7.6 - issued: december 18, 2008 ? all changes from the previous revision are in red ? section 19, updated sales and technical support addresses x40a-a-001-07 revision 7.5 - issued: february 13, 2008 ? all changes from the previous revision are in red ? release as revision 7.5 to align with japan numbering ? section 18 references - remove references to obsolete application notes and change ?interfacing to the motorola mcf5307...? to ?interfacing to the freescale mcf5307...? x40a-a-001-07 revision 7.04 - released: september 17, 2007 ? all changes from the previous revision are in red ? section 18, updated refereces ? section 19, updated sales and technical support addresses x40a-a-001-07 revision 7.03 - released: june 13, 2007 ? all changes from the previous revision are in red ? section 4.2.1, corrected the pfbga pin# listing for the db[15:0] pin description x40a-a-001-07 revision 7.02 - released: february 01, 2007 ? all changes from the previous revision are in red ? section 6.5, changed formula for vps from ?reg[002ch] bits 9-0? to ?reg[003ch] bits 9-0? ? section 6.5.1, changed formula for vps from ?reg[002ch] bits 9-0? to ?reg[003ch] bits 9-0? x40a-a-001-07 revision 7.01, released: october 3, 2006 ? all changes from the previous revision are in red ? reg[04h] bit 0 - remove reference to cnf7 page 184 epson research and development vancouver design center s1d13a05 hardware functional specification x40a-a-001-07 issue date: 2012/02/27 revision 7.7 ? section 19 sales and technical support - update the addresses for north america and singapore x40a-a-001-07 revision 7, released: july 7, 2006 ? all changes from the previous revision are in red ? add section 6.2 reset# timing x40a-a-001-06 revision 6.01 ? section 3.1, figure 3-1, changed system diagram for generic #1 so that bs# pin is connected to iovdd instead of vss (gnd) ? section 4.2.1, table 4-2, changed bs# pin description for generic #1 so that bs# pin is connected to iovdd instead of vss (gnd) ? reg[10h] bits 4-0, updated the bits-per-pixel bit description and clarified the color depth table x40a-a-001-06 revision 6.0 ? released as revision 6.0 x40a-a-001-05 revision 5.01 ? section 2.9, added qfp package to features ? section 4.1.2, added qfp package pin diagram ? section 4.2, added qfp package pin descriptions ? section 18, added qfp package mechanical drawing x40a-a-001-05 revision 5.0 ? released as revision 5.0 x40a-a-001-04 revision 4.01 ? section 4.2.2, for drdy pin description, removed description for hr-tft (not used) |
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